Lines Matching refs:UL
39 #define FLASH1_BASE UL(0x0c000000)
40 #define FLASH1_SIZE UL(0x04000000)
42 #define PSRAM_BASE UL(0x14000000)
43 #define PSRAM_SIZE UL(0x04000000)
45 #define VRAM_BASE UL(0x18000000)
46 #define VRAM_SIZE UL(0x02000000)
49 #define DEVICE0_BASE UL(0x20000000)
50 #define DEVICE0_SIZE UL(0x0c200000)
57 #define DEVICE1_BASE UL(0x2e000000)
58 #define DEVICE1_SIZE UL(0x1A00000)
72 #define NSRAM_BASE UL(0x2e000000)
73 #define NSRAM_SIZE UL(0x10000)
76 #define DEVICE2_BASE UL(0x7fe00000)
77 #define DEVICE2_SIZE UL(0x00200000)
79 #define PCIE_EXP_BASE UL(0x40000000)
80 #define TZRNG_BASE UL(0x7fe60000)
83 #define TRUSTED_NVCTR_BASE UL(0x7fe70000)
84 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000))
85 #define TFW_NVCTR_SIZE UL(4)
86 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004))
87 #define NTFW_CTR_SIZE UL(4)
90 #define SOC_KEYS_BASE UL(0x7fe80000)
91 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000))
92 #define TZ_PUB_KEY_HASH_SIZE UL(32)
93 #define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020))
94 #define HU_KEY_SIZE UL(16)
95 #define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044))
96 #define END_KEY_SIZE UL(32)
115 #define PWRC_BASE UL(0x1c100000)
131 #define VE_GICD_BASE UL(0x2c001000)
132 #define VE_GICC_BASE UL(0x2c002000)
133 #define VE_GICH_BASE UL(0x2c004000)
134 #define VE_GICV_BASE UL(0x2c006000)
137 #define BASE_GICD_BASE UL(0x2f000000)
138 #define BASE_GICD_SIZE UL(0x10000)
139 #define BASE_GICR_BASE UL(0x2f100000)
143 #define BASE_GICR_SIZE UL(0x40000)
145 #define BASE_GICR_SIZE UL(0x20000)
148 #define BASE_GICC_BASE UL(0x2c000000)
149 #define BASE_GICH_BASE UL(0x2c010000)
150 #define BASE_GICV_BASE UL(0x2c02f000)