Lines Matching refs:UL
33 #define PLAT_CRYPTOCELL_BASE UL(0x60050000)
44 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
50 #define NSRAM_BASE UL(0x2e000000)
51 #define NSRAM_SIZE UL(0x00008000) /* 32KB */
66 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
73 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
74 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
75 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000)
77 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
78 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
79 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0)
89 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000)
91 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000)
133 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
135 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000)
144 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
146 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
148 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
151 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
160 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000)
169 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000)
177 # define PLATFORM_STACK_SIZE UL(0x1000)
179 # define PLATFORM_STACK_SIZE UL(0x440)
183 # define PLATFORM_STACK_SIZE UL(0x1000)
185 # define PLATFORM_STACK_SIZE UL(0x400)
188 # define PLATFORM_STACK_SIZE UL(0x400)
191 # define PLATFORM_STACK_SIZE UL(0x800)
193 # define PLATFORM_STACK_SIZE UL(0x400)
196 # define PLATFORM_STACK_SIZE UL(0x440)
206 #define PLAT_ARM_CCI_BASE UL(0x2c090000)
214 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000)
235 #define PLAT_ARM_GICD_BASE UL(0x2c010000)
236 #define PLAT_ARM_GICC_BASE UL(0x2c02f000)
237 #define PLAT_ARM_GICH_BASE UL(0x2c04f000)
238 #define PLAT_ARM_GICV_BASE UL(0x2c06f000)
241 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000)
255 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80))
297 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000)