Lines Matching refs:data
22 unsigned int data; in init_pll() local
24 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
25 data |= 0x1; in init_pll()
26 mmio_write_32((0xf7032000 + 0x000), data); in init_pll()
28 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
29 } while (!(data & (1 << 28))); in init_pll()
31 data = mmio_read_32((0xf7800000 + 0x000)); in init_pll()
32 data &= ~0x007; in init_pll()
33 data |= 0x004; in init_pll()
34 mmio_write_32((0xf7800000 + 0x000), data); in init_pll()
36 data = mmio_read_32((0xf7800000 + 0x014)); in init_pll()
37 data &= 0x007; in init_pll()
38 } while (data != 0x004); in init_pll()
56 data = mmio_read_32(0xf7032000 + 0x050); in init_pll()
57 data |= 1 << 28; in init_pll()
58 mmio_write_32(0xf7032000 + 0x050, data); in init_pll()
78 unsigned int data, tmp; in init_freq() local
90 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
91 data |= (3 << 12); in init_freq()
92 mmio_write_32((0xf7032000 + 0x110), data); in init_freq()
94 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
95 data |= (1 << 4); in init_freq()
96 mmio_write_32((0xf7032000 + 0x110), data); in init_freq()
99 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
100 data &= ~0x7; in init_freq()
101 data |= 0x5; in init_freq()
102 mmio_write_32((0xf7032000 + 0x110), data); in init_freq()
108 data = mmio_read_32((0xf6504000 + 0x008)); in init_freq()
109 data &= (3 << 20); in init_freq()
110 } while (data != (3 << 20)); in init_freq()
115 data = mmio_read_32((0xf6504000 + 0x054)); in init_freq()
116 data &= ~((1 << 0) | (1 << 11)); in init_freq()
117 mmio_write_32((0xf6504000 + 0x054), data); in init_freq()
120 data = mmio_read_32((0xf7032000 + 0x104)); in init_freq()
121 data &= ~(3 << 8); in init_freq()
122 data |= (1 << 8); in init_freq()
123 mmio_write_32((0xf7032000 + 0x104), data); in init_freq()
125 data = mmio_read_32((0xf7032000 + 0x100)); in init_freq()
126 data |= (1 << 0); in init_freq()
127 mmio_write_32((0xf7032000 + 0x100), data); in init_freq()
131 data = mmio_read_32((0xf7032000 + 0x100)); in init_freq()
132 data &= (1 << 2); in init_freq()
133 } while (data != (1 << 2)); in init_freq()
135 data = mmio_read_32((0xf6504000 + 0x06c)); in init_freq()
136 data &= ~0xffff; in init_freq()
137 data |= 0x56; in init_freq()
138 mmio_write_32((0xf6504000 + 0x06c), data); in init_freq()
140 data = mmio_read_32((0xf6504000 + 0x06c)); in init_freq()
141 data &= ~(0xffffffu << 8); in init_freq()
142 data |= 0xc7a << 8; in init_freq()
143 mmio_write_32((0xf6504000 + 0x06c), data); in init_freq()
145 data = mmio_read_32((0xf6504000 + 0x058)); in init_freq()
146 data &= ((1 << 13) - 1); in init_freq()
147 data |= 0xccb; in init_freq()
148 mmio_write_32((0xf6504000 + 0x058), data); in init_freq()
155 data = mmio_read_32((0xf6504000 + 0x054)); in init_freq()
156 data &= ~(0xf << 12); in init_freq()
157 data |= 1 << 12; in init_freq()
158 mmio_write_32((0xf6504000 + 0x054), data); in init_freq()
162 data = mmio_read_32((0xf7032000 + 0x000)); in init_freq()
163 data &= ~(1 << 0); in init_freq()
164 mmio_write_32((0xf7032000 + 0x000), data); in init_freq()
168 data = mmio_read_32((0xf7032000 + 0x134)); in init_freq()
171 data = mmio_read_32((0xf7032000 + 0x000)); in init_freq()
172 data |= (1 << 0); in init_freq()
173 mmio_write_32((0xf7032000 + 0x000), data); in init_freq()
176 data = mmio_read_32((0xf7032000 + 0x378)); in init_freq()
177 data &= ~((1 << 7) - 1); in init_freq()
178 data |= 0x6b; in init_freq()
179 mmio_write_32((0xf7032000 + 0x378), data); in init_freq()
182 data = mmio_read_32((0xf7032000 + 0x378)); in init_freq()
183 tmp = data & 0x7f; in init_freq()
184 data = (data & (0x7f << 8)) >> 8; in init_freq()
185 if (data != tmp) in init_freq()
187 data = mmio_read_32((0xf7032000 + 0x37c)); in init_freq()
188 } while (!(data & 1)); in init_freq()
190 data = mmio_read_32((0xf7032000 + 0x104)); in init_freq()
191 data &= ~((3 << 0) | in init_freq()
195 data |= cpuext_cfg | (ddr_cfg << 8); in init_freq()
196 mmio_write_32((0xf7032000 + 0x104), data); in init_freq()
200 data = mmio_read_32((0xf7032000 + 0x104)); in init_freq()
201 tmp = (data & (3 << 16)) >> 16; in init_freq()
204 tmp = (data & (3 << 24)) >> 24; in init_freq()
207 data = mmio_read_32((0xf7032000 + 0x000)); in init_freq()
208 data &= 1 << 28; in init_freq()
209 } while (!data); in init_freq()
211 data = mmio_read_32((0xf7032000 + 0x100)); in init_freq()
212 data &= ~(1 << 0); in init_freq()
213 mmio_write_32((0xf7032000 + 0x100), data); in init_freq()
216 data = mmio_read_32((0xf7032000 + 0x100)); in init_freq()
217 data &= (1 << 1); in init_freq()
218 } while (data != (1 << 1)); in init_freq()
221 data = mmio_read_32((0xf6504000 + 0x054)); in init_freq()
222 data &= ~(1 << 28); in init_freq()
223 mmio_write_32((0xf6504000 + 0x054), data); in init_freq()
226 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
227 data &= ~((1 << 4) | in init_freq()
229 mmio_write_32((0xf7032000 + 0x110), data); in init_freq()
234 unsigned int data, i; in cat_533mhz_800mhz() local
238 data = mmio_read_32((0xf712c000 + 0x1c8)); in cat_533mhz_800mhz()
239 data &= 0xfffff0f0; in cat_533mhz_800mhz()
240 data |= 0x100f01; in cat_533mhz_800mhz()
241 mmio_write_32((0xf712c000 + 0x1c8), data); in cat_533mhz_800mhz()
245 data = (i << 0x10) + i; in cat_533mhz_800mhz()
246 mmio_write_32((0xf712c000 + 0x140), data); in cat_533mhz_800mhz()
247 mmio_write_32((0xf712c000 + 0x144), data); in cat_533mhz_800mhz()
248 mmio_write_32((0xf712c000 + 0x148), data); in cat_533mhz_800mhz()
249 mmio_write_32((0xf712c000 + 0x14c), data); in cat_533mhz_800mhz()
250 mmio_write_32((0xf712c000 + 0x150), data); in cat_533mhz_800mhz()
253 data = mmio_read_32((0xf712c000 + 0x070)); in cat_533mhz_800mhz()
254 data |= 0x80000; in cat_533mhz_800mhz()
255 mmio_write_32((0xf712c000 + 0x070), data); in cat_533mhz_800mhz()
256 data = mmio_read_32((0xf712c000 + 0x070)); in cat_533mhz_800mhz()
257 data &= 0xfff7ffff; in cat_533mhz_800mhz()
258 mmio_write_32((0xf712c000 + 0x070), data); in cat_533mhz_800mhz()
265 data = mmio_read_32((0xf712c000 + 0x004)); in cat_533mhz_800mhz()
266 } while (data & 1); in cat_533mhz_800mhz()
268 data = mmio_read_32((0xf712c000 + 0x008)); in cat_533mhz_800mhz()
269 if ((data & 0x400) == 0) { in cat_533mhz_800mhz()
274 data = mmio_read_32((0xf712c000 + 0x1d4)); in cat_533mhz_800mhz()
275 if ((data & 0x1f00) && ((data & 0x1f) == 0)) { in cat_533mhz_800mhz()
304 unsigned int data, rdet, bdl[4]; in ddrx_rdet() local
306 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_rdet()
307 data &= 0xf800ffff; in ddrx_rdet()
308 data |= 0x8f0000; in ddrx_rdet()
309 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_rdet()
311 data = mmio_read_32((0xf712c000 + 0x0dc)); in ddrx_rdet()
312 data &= 0xfffffff0; in ddrx_rdet()
313 data |= 0xf; in ddrx_rdet()
314 mmio_write_32((0xf712c000 + 0x0dc), data); in ddrx_rdet()
317 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_rdet()
318 data |= 0x80000; in ddrx_rdet()
319 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_rdet()
320 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_rdet()
321 data &= 0xfff7ffff; in ddrx_rdet()
322 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_rdet()
327 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_rdet()
328 data &= ~0xf0000000; in ddrx_rdet()
329 data |= 0x80000000; in ddrx_rdet()
330 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_rdet()
334 data = mmio_read_32((0xf712c000 + 0x004)); in ddrx_rdet()
335 } while (!(data & 1)); in ddrx_rdet()
336 data = mmio_read_32((0xf712c000 + 0x008)); in ddrx_rdet()
337 if (data & 0x100) in ddrx_rdet()
345 data = mmio_read_32((0xf712c000 + 0x22c)); in ddrx_rdet()
346 data &= ~0x7f; in ddrx_rdet()
347 data |= bdl[0]; in ddrx_rdet()
348 mmio_write_32((0xf712c000 + 0x22c), data); in ddrx_rdet()
349 data = mmio_read_32((0xf712c000 + 0x2ac)); in ddrx_rdet()
350 data &= ~0x7f; in ddrx_rdet()
351 data |= bdl[1]; in ddrx_rdet()
352 mmio_write_32((0xf712c000 + 0x2ac), data); in ddrx_rdet()
353 data = mmio_read_32((0xf712c000 + 0x32c)); in ddrx_rdet()
354 data &= ~0x7f; in ddrx_rdet()
355 data |= bdl[2]; in ddrx_rdet()
356 mmio_write_32((0xf712c000 + 0x32c), data); in ddrx_rdet()
357 data = mmio_read_32((0xf712c000 + 0x3ac)); in ddrx_rdet()
358 data &= ~0x7f; in ddrx_rdet()
359 data |= bdl[3]; in ddrx_rdet()
360 mmio_write_32((0xf712c000 + 0x3ac), data); in ddrx_rdet()
363 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_rdet()
364 data |= 0x80000; in ddrx_rdet()
365 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_rdet()
366 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_rdet()
367 data &= 0xfff7ffff; in ddrx_rdet()
368 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_rdet()
373 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_rdet()
374 data &= ~0xf0000000; in ddrx_rdet()
375 data |= 0x40000000; in ddrx_rdet()
376 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_rdet()
379 data = mmio_read_32((0xf712c000 + 0x004)); in ddrx_rdet()
380 } while (data & 1); in ddrx_rdet()
382 data = mmio_read_32((0xf712c000 + 0x008)); in ddrx_rdet()
383 rdet = data & 0x100; in ddrx_rdet()
394 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_rdet()
395 data &= ~0xf0000000; in ddrx_rdet()
396 data |= 0x30000000; in ddrx_rdet()
397 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_rdet()
401 data = mmio_read_32((0xf712c000 + 0x004)); in ddrx_rdet()
402 } while (data & 1); in ddrx_rdet()
403 data = mmio_read_32((0xf712c000 + 0x008)); in ddrx_rdet()
404 if (data & 0x100) in ddrx_rdet()
410 unsigned int data, wdet, zero_bdl = 0, dq[4]; in ddrx_wdet() local
413 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_wdet()
414 data &= ~0xf; in ddrx_wdet()
415 data |= 0xf; in ddrx_wdet()
416 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_wdet()
418 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_wdet()
419 data |= 0x80000; in ddrx_wdet()
420 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_wdet()
421 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_wdet()
422 data &= ~0x80000; in ddrx_wdet()
423 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_wdet()
427 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_wdet()
428 data &= ~0xf000; in ddrx_wdet()
429 data |= 0x8000; in ddrx_wdet()
430 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_wdet()
433 data = mmio_read_32((0xf712c000 + 0x004)); in ddrx_wdet()
434 } while (data & 1); in ddrx_wdet()
435 data = mmio_read_32((0xf712c000 + 0x008)); in ddrx_wdet()
436 if (data & 0x200) in ddrx_wdet()
450 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_wdet()
451 data |= 0x80000; in ddrx_wdet()
452 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_wdet()
453 data = mmio_read_32((0xf712c000 + 0x070)); in ddrx_wdet()
454 data &= ~0x80000; in ddrx_wdet()
455 mmio_write_32((0xf712c000 + 0x070), data); in ddrx_wdet()
459 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_wdet()
460 data &= ~0xf000; in ddrx_wdet()
461 data |= 0x4000; in ddrx_wdet()
462 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_wdet()
465 data = mmio_read_32((0xf712c000 + 0x004)); in ddrx_wdet()
466 } while (data & 1); in ddrx_wdet()
468 data = mmio_read_32((0xf712c000 + 0x008)); in ddrx_wdet()
469 wdet = data & 0x200; in ddrx_wdet()
477 data = mmio_read_32((0xf712c000 + 0x210 + i * 0x80)); in ddrx_wdet()
478 if ((!(data & 0x1f)) || (!(data & 0x1f00)) || in ddrx_wdet()
479 (!(data & 0x1f0000)) || (!(data & 0x1f000000))) in ddrx_wdet()
481 data = mmio_read_32((0xf712c000 + 0x214 + i * 0x80)); in ddrx_wdet()
482 if ((!(data & 0x1f)) || (!(data & 0x1f00)) || in ddrx_wdet()
483 (!(data & 0x1f0000)) || (!(data & 0x1f000000))) in ddrx_wdet()
485 data = mmio_read_32((0xf712c000 + 0x218 + i * 0x80)); in ddrx_wdet()
486 if (!(data & 0x1f)) in ddrx_wdet()
501 data = mmio_read_32((0xf712c000 + 0x0d0)); in ddrx_wdet()
502 data &= ~0xf000; in ddrx_wdet()
503 data |= 0x3000; in ddrx_wdet()
504 mmio_write_32((0xf712c000 + 0x0d0), data); in ddrx_wdet()
507 data = mmio_read_32((0xf712c000 + 0x004)); in ddrx_wdet()
508 } while (data & 1); in ddrx_wdet()
509 data = mmio_read_32((0xf712c000 + 0x008)); in ddrx_wdet()
510 if (data & 0x200) in ddrx_wdet()
516 unsigned int data; in set_ddrc_150mhz() local
520 data = mmio_read_32((0xf7032000 + 0x104)); in set_ddrc_150mhz()
521 data &= 0xfffffcff; in set_ddrc_150mhz()
522 mmio_write_32((0xf7032000 + 0x104), data); in set_ddrc_150mhz()
541 data = mmio_read_32((0xf712c000 + 0x078)); in set_ddrc_150mhz()
542 data |= 4; in set_ddrc_150mhz()
543 mmio_write_32((0xf712c000 + 0x078), data); in set_ddrc_150mhz()
545 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_150mhz()
546 data &= 0xfffffffe; in set_ddrc_150mhz()
547 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_150mhz()
551 data = mmio_read_32((0xf712c000 + 0x1e4)); in set_ddrc_150mhz()
552 data &= 0xffffff00; in set_ddrc_150mhz()
553 mmio_write_32((0xf712c000 + 0x1e4), data); in set_ddrc_150mhz()
561 data = mmio_read_32((0xf712c000 + 0x070)); in set_ddrc_150mhz()
562 data &= 0xffff0000; in set_ddrc_150mhz()
563 data |= 0x184; in set_ddrc_150mhz()
564 mmio_write_32((0xf712c000 + 0x070), data); in set_ddrc_150mhz()
565 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_150mhz()
566 data &= 0xbfffffff; in set_ddrc_150mhz()
567 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_150mhz()
568 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_150mhz()
569 data &= ~0x10; in set_ddrc_150mhz()
570 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_150mhz()
571 data = mmio_read_32((0xf712c000 + 0x080)); in set_ddrc_150mhz()
572 data &= ~0x2000; in set_ddrc_150mhz()
573 mmio_write_32((0xf712c000 + 0x080), data); in set_ddrc_150mhz()
595 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_150mhz()
596 } while (data & 1); in set_ddrc_150mhz()
597 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_150mhz()
598 if (data & 8) { in set_ddrc_150mhz()
603 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_150mhz()
604 data |= 1; in set_ddrc_150mhz()
605 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_150mhz()
608 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_150mhz()
609 } while (data & 1); in set_ddrc_150mhz()
611 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_150mhz()
612 if (data & 0x8) in set_ddrc_150mhz()
617 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_150mhz()
618 data &= ~0xf; in set_ddrc_150mhz()
619 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_150mhz()
625 unsigned int data; in set_ddrc_266mhz() local
629 data = mmio_read_32((0xf7032000 + 0x104)); in set_ddrc_266mhz()
630 data &= 0xfffffcff; in set_ddrc_266mhz()
631 mmio_write_32((0xf7032000 + 0x104), data); in set_ddrc_266mhz()
650 data = mmio_read_32((0xf712c000 + 0x078)); in set_ddrc_266mhz()
651 data |= 4; in set_ddrc_266mhz()
652 mmio_write_32((0xf712c000 + 0x078), data); in set_ddrc_266mhz()
654 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_266mhz()
655 data &= 0xfffffffe; in set_ddrc_266mhz()
656 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_266mhz()
660 data = mmio_read_32((0xf712c000 + 0x1e4)); in set_ddrc_266mhz()
661 data &= 0xffffff00; in set_ddrc_266mhz()
662 mmio_write_32((0xf712c000 + 0x1e4), data); in set_ddrc_266mhz()
670 data = mmio_read_32((0xf712c000 + 0x070)); in set_ddrc_266mhz()
671 data &= 0xffff0000; in set_ddrc_266mhz()
672 data |= 0x184; in set_ddrc_266mhz()
673 mmio_write_32((0xf712c000 + 0x070), data); in set_ddrc_266mhz()
674 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_266mhz()
675 data &= 0xbfffffff; in set_ddrc_266mhz()
676 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_266mhz()
677 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_266mhz()
678 data &= ~0x10; in set_ddrc_266mhz()
679 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_266mhz()
680 data = mmio_read_32((0xf712c000 + 0x080)); in set_ddrc_266mhz()
681 data &= ~0x2000; in set_ddrc_266mhz()
682 mmio_write_32((0xf712c000 + 0x080), data); in set_ddrc_266mhz()
704 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_266mhz()
705 } while (data & 1); in set_ddrc_266mhz()
706 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_266mhz()
707 if (data & 8) { in set_ddrc_266mhz()
712 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_266mhz()
713 data |= 1; in set_ddrc_266mhz()
714 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_266mhz()
717 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_266mhz()
718 } while (data & 1); in set_ddrc_266mhz()
720 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_266mhz()
721 if (data & 0x8) in set_ddrc_266mhz()
726 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_266mhz()
727 data &= ~0xf; in set_ddrc_266mhz()
728 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_266mhz()
734 unsigned int data; in set_ddrc_400mhz() local
738 data = mmio_read_32((0xf7032000 + 0x104)); in set_ddrc_400mhz()
739 data &= 0xfffffcff; in set_ddrc_400mhz()
740 mmio_write_32((0xf7032000 + 0x104), data); in set_ddrc_400mhz()
759 data = mmio_read_32((0xf712c000 + 0x078)); in set_ddrc_400mhz()
760 data |= 4; in set_ddrc_400mhz()
761 mmio_write_32((0xf712c000 + 0x078), data); in set_ddrc_400mhz()
763 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_400mhz()
764 data &= 0xfffffffe; in set_ddrc_400mhz()
765 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_400mhz()
769 data = mmio_read_32((0xf712c000 + 0x1e4)); in set_ddrc_400mhz()
770 data &= 0xffffff00; in set_ddrc_400mhz()
771 mmio_write_32((0xf712c000 + 0x1e4), data); in set_ddrc_400mhz()
779 data = mmio_read_32((0xf712c000 + 0x070)); in set_ddrc_400mhz()
780 data &= 0xffff0000; in set_ddrc_400mhz()
781 data |= 0x184; in set_ddrc_400mhz()
782 mmio_write_32((0xf712c000 + 0x070), data); in set_ddrc_400mhz()
783 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_400mhz()
784 data &= 0xbfffffff; in set_ddrc_400mhz()
785 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_400mhz()
786 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_400mhz()
787 data &= ~0x10; in set_ddrc_400mhz()
788 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_400mhz()
789 data = mmio_read_32((0xf712c000 + 0x080)); in set_ddrc_400mhz()
790 data &= ~0x2000; in set_ddrc_400mhz()
791 mmio_write_32((0xf712c000 + 0x080), data); in set_ddrc_400mhz()
813 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_400mhz()
814 } while (data & 1); in set_ddrc_400mhz()
815 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_400mhz()
816 if (data & 8) { in set_ddrc_400mhz()
821 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_400mhz()
822 data |= 1; in set_ddrc_400mhz()
823 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_400mhz()
826 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_400mhz()
827 } while (data & 1); in set_ddrc_400mhz()
829 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_400mhz()
830 if (data & 0x8) in set_ddrc_400mhz()
835 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_400mhz()
836 data &= ~0xf; in set_ddrc_400mhz()
837 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_400mhz()
843 unsigned int data; in set_ddrc_533mhz() local
847 data = mmio_read_32((0xf7032000 + 0x104)); in set_ddrc_533mhz()
848 data |= 0x100; in set_ddrc_533mhz()
849 mmio_write_32((0xf7032000 + 0x104), data); in set_ddrc_533mhz()
868 data = mmio_read_32((0xf712c000 + 0x078)); in set_ddrc_533mhz()
869 data |= 4; in set_ddrc_533mhz()
870 mmio_write_32((0xf712c000 + 0x078), data); in set_ddrc_533mhz()
872 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_533mhz()
873 data &= 0xfffffffe; in set_ddrc_533mhz()
874 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_533mhz()
878 data = mmio_read_32((0xf712c000 + 0x1e4)); in set_ddrc_533mhz()
879 data &= 0xffffff00; in set_ddrc_533mhz()
880 mmio_write_32((0xf712c000 + 0x1e4), data); in set_ddrc_533mhz()
888 data = mmio_read_32((0xf712c000 + 0x070)); in set_ddrc_533mhz()
889 data &= 0xffff0000; in set_ddrc_533mhz()
890 data |= 0x305; in set_ddrc_533mhz()
891 mmio_write_32((0xf712c000 + 0x070), data); in set_ddrc_533mhz()
892 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_533mhz()
893 data |= 0x40000000; in set_ddrc_533mhz()
894 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_533mhz()
895 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_533mhz()
896 data &= ~0x10; in set_ddrc_533mhz()
897 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_533mhz()
898 data = mmio_read_32((0xf712c000 + 0x080)); in set_ddrc_533mhz()
899 data &= ~0x2000; in set_ddrc_533mhz()
900 mmio_write_32((0xf712c000 + 0x080), data); in set_ddrc_533mhz()
910 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_533mhz()
911 } while (data & 1); in set_ddrc_533mhz()
912 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_533mhz()
913 if (data & 0x7fe) { in set_ddrc_533mhz()
933 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_533mhz()
934 } while (data & 1); in set_ddrc_533mhz()
935 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_533mhz()
936 if (data & 0x7fe) { in set_ddrc_533mhz()
943 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_533mhz()
944 data |= 1; in set_ddrc_533mhz()
945 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_533mhz()
948 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_533mhz()
949 } while (data & 1); in set_ddrc_533mhz()
951 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_533mhz()
952 if (data & 0x7fe) in set_ddrc_533mhz()
957 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_533mhz()
958 data &= ~0xf; in set_ddrc_533mhz()
959 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_533mhz()
965 unsigned int data; in set_ddrc_800mhz() local
969 data = mmio_read_32((0xf7032000 + 0x104)); in set_ddrc_800mhz()
970 data &= 0xfffffcff; in set_ddrc_800mhz()
971 mmio_write_32((0xf7032000 + 0x104), data); in set_ddrc_800mhz()
990 data = mmio_read_32((0xf712c000 + 0x078)); in set_ddrc_800mhz()
991 data |= 4; in set_ddrc_800mhz()
992 mmio_write_32((0xf712c000 + 0x078), data); in set_ddrc_800mhz()
994 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_800mhz()
995 data &= 0xfffffffe; in set_ddrc_800mhz()
996 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_800mhz()
1000 data = mmio_read_32((0xf712c000 + 0x1e4)); in set_ddrc_800mhz()
1001 data &= 0xffffff00; in set_ddrc_800mhz()
1002 mmio_write_32((0xf712c000 + 0x1e4), data); in set_ddrc_800mhz()
1010 data = mmio_read_32((0xf712c000 + 0x070)); in set_ddrc_800mhz()
1011 data &= 0xffff0000; in set_ddrc_800mhz()
1012 data |= 0x507; in set_ddrc_800mhz()
1013 mmio_write_32((0xf712c000 + 0x070), data); in set_ddrc_800mhz()
1014 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_800mhz()
1015 data |= 0x40000000; in set_ddrc_800mhz()
1016 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_800mhz()
1017 data = mmio_read_32((0xf712c000 + 0x020)); in set_ddrc_800mhz()
1018 data &= 0xffffffef; in set_ddrc_800mhz()
1019 mmio_write_32((0xf712c000 + 0x020), data); in set_ddrc_800mhz()
1020 data = mmio_read_32((0xf712c000 + 0x080)); in set_ddrc_800mhz()
1021 data &= 0xffffdfff; in set_ddrc_800mhz()
1022 mmio_write_32((0xf712c000 + 0x080), data); in set_ddrc_800mhz()
1032 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_800mhz()
1033 } while (data & 1); in set_ddrc_800mhz()
1034 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_800mhz()
1035 if (data & 0x7fe) { in set_ddrc_800mhz()
1055 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_800mhz()
1056 } while (data & 1); in set_ddrc_800mhz()
1057 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_800mhz()
1058 if (data & 0x7fe) { in set_ddrc_800mhz()
1065 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_800mhz()
1066 data |= 1; in set_ddrc_800mhz()
1067 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_800mhz()
1070 data = mmio_read_32((0xf712c000 + 0x004)); in set_ddrc_800mhz()
1071 } while (data & 1); in set_ddrc_800mhz()
1073 data = mmio_read_32((0xf712c000 + 0x008)); in set_ddrc_800mhz()
1074 if (data & 0x7fe) in set_ddrc_800mhz()
1079 data = mmio_read_32((0xf712c000 + 0x048)); in set_ddrc_800mhz()
1080 data &= ~0xf; in set_ddrc_800mhz()
1081 mmio_write_32((0xf712c000 + 0x048), data); in set_ddrc_800mhz()
1087 unsigned int data; in ddrc_common_init() local
1103 data = mmio_read_32((0xf7128000 + 0x280)); in ddrc_common_init()
1104 data |= 1 << 7; in ddrc_common_init()
1105 mmio_write_32((0xf7128000 + 0x280), data); in ddrc_common_init()
1113 data = mmio_read_32((0xf712c000 + 0x080)); in ddrc_common_init()
1114 data &= 0xffff; in ddrc_common_init()
1115 data |= 0x4002000; in ddrc_common_init()
1116 mmio_write_32((0xf712c000 + 0x080), data); in ddrc_common_init()
1119 data = mmio_read_32((0xf7128000 + 0x294)); in ddrc_common_init()
1120 } while (data & 1); in ddrc_common_init()
1127 unsigned int data; in dienum_det_and_rowcol_cfg() local
1133 data = mmio_read_32((0xf7128000 + 0x00c)); in dienum_det_and_rowcol_cfg()
1134 } while (data & 1); in dienum_det_and_rowcol_cfg()
1135 data = mmio_read_32((0xf7128000 + 0x4a8)) & 0xfc; in dienum_det_and_rowcol_cfg()
1136 switch (data) { in dienum_det_and_rowcol_cfg()
1162 if (!data) in dienum_det_and_rowcol_cfg()
1169 unsigned int data, mr5, mr6, mr7; in detect_ddr_chip_info() local
1176 data = mmio_read_32((0xf7128000 + 0x00c)); in detect_ddr_chip_info()
1177 } while (data & 1); in detect_ddr_chip_info()
1179 data = mmio_read_32((0xf7128000 + 0x4a8)); in detect_ddr_chip_info()
1180 mr5 = data & 0xff; in detect_ddr_chip_info()
1200 data = mmio_read_32((0xf7128000 + 0x00c)); in detect_ddr_chip_info()
1201 } while (data & 1); in detect_ddr_chip_info()
1202 data = mmio_read_32((0xf7128000 + 0x4a8)); in detect_ddr_chip_info()
1203 mr6 = data & 0xff; in detect_ddr_chip_info()
1208 data = mmio_read_32((0xf7128000 + 0x00c)); in detect_ddr_chip_info()
1209 } while (data & 1); in detect_ddr_chip_info()
1210 data = mmio_read_32((0xf7128000 + 0x4a8)); in detect_ddr_chip_info()
1211 mr7 = data & 0xff; in detect_ddr_chip_info()
1212 data = mr5 + (mr6 << 8) + (mr7 << 16); in detect_ddr_chip_info()
1213 return data; in detect_ddr_chip_info()
1329 unsigned int data; in init_ddr() local
1333 data = mmio_read_32((0xf7032000 + 0x030)); in init_ddr()
1334 data |= 1; in init_ddr()
1335 mmio_write_32((0xf7032000 + 0x030), data); in init_ddr()
1336 data = mmio_read_32((0xf7032000 + 0x010)); in init_ddr()
1337 data |= 1; in init_ddr()
1338 mmio_write_32((0xf7032000 + 0x010), data); in init_ddr()
1342 data = mmio_read_32((0xf7032000 + 0x030)); in init_ddr()
1343 data &= 3 << 28; in init_ddr()
1344 } while (data != (3 << 28)); in init_ddr()
1346 data = mmio_read_32((0xf7032000 + 0x010)); in init_ddr()
1347 data &= 3 << 28; in init_ddr()
1348 } while (data != (3 << 28)); in init_ddr()
1357 unsigned int port, data; in init_ddrc_qos() local
1386 data = mmio_read_32((0xf7124000 + 0x09c)); in init_ddrc_qos()
1387 data &= ~0xff0000; in init_ddrc_qos()
1388 data |= 0x400000; in init_ddrc_qos()
1389 mmio_write_32((0xf7124000 + 0x09c), data); in init_ddrc_qos()
1390 data = mmio_read_32((0xf7124000 + 0x0ac)); in init_ddrc_qos()
1391 data &= ~0xff0000; in init_ddrc_qos()
1392 data |= 0x400000; in init_ddrc_qos()
1393 mmio_write_32((0xf7124000 + 0x0ac), data); in init_ddrc_qos()
1410 uint32_t data; in hikey_ddr_init() local
1425 data = mmio_read_32(0xf7032000 + 0x010); in hikey_ddr_init()
1426 data &= ~0x1; in hikey_ddr_init()
1427 mmio_write_32(0xf7032000 + 0x010, data); in hikey_ddr_init()
1429 data = mmio_read_32(0xf7032000 + 0x030); in hikey_ddr_init()
1430 data &= ~0x1; in hikey_ddr_init()
1431 mmio_write_32(0xf7032000 + 0x030, data); in hikey_ddr_init()
1433 data = mmio_read_32(0xf7032000 + 0x010); in hikey_ddr_init()
1434 data &= ~0x1; in hikey_ddr_init()
1435 mmio_write_32(0xf7032000 + 0x010, data); in hikey_ddr_init()
1436 data = mmio_read_32(0xf7032000 + 0x030); in hikey_ddr_init()
1437 data &= ~0x1; in hikey_ddr_init()
1438 mmio_write_32(0xf7032000 + 0x030, data); in hikey_ddr_init()