Lines Matching refs:IMX_GPC_BASE
47 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
52 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
60 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_on()
67 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
69 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); in imx_set_cpu_pwr_on()
72 while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0) in imx_set_cpu_pwr_on()
76 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
87 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
90 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
93 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
96 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
111 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
112 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
113 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK | in imx_a53_plat_slot_config()
115 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
117 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
118 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
119 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | in imx_a53_plat_slot_config()
121 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
132 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
134 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
144 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, in imx_set_cluster_powerdown()
147 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state)); in imx_set_cluster_powerdown()
150 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
158 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
163 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); in imx_set_cluster_powerdown()
164 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); in imx_set_cluster_powerdown()
167 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), in imx_set_cluster_powerdown()
190 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), in imx_set_sys_wakeup()
193 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, in imx_set_sys_wakeup()
204 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, in imx_set_sys_wakeup()
225 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_set_sys_lpm()
233 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_set_sys_lpm()
244 mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | in imx_set_rbc_count()
250 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | in imx_clear_rbc_count()