Lines Matching refs:IMX_GPC_BASE
25 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_pwr_off()
31 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
41 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
44 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
47 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
50 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
60 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN); in imx_pup_pdn_slot_config()
62 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP); in imx_pup_pdn_slot_config()
64 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core)); in imx_pup_pdn_slot_config()
66 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, in imx_pup_pdn_slot_config()
69 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
70 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
71 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
72 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, in imx_pup_pdn_slot_config()
82 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_set_cluster_powerdown()
85 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_set_cluster_powerdown()
88 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP); in imx_set_cluster_powerdown()
91 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
96 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
101 mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
104 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
109 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_set_cluster_powerdown()
112 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_set_cluster_powerdown()
115 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK); in imx_set_cluster_powerdown()
118 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
122 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
132 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
133 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
134 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); in imx_gpc_init()
135 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
136 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
142 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53, 0xFFFFFFFE); in imx_gpc_init()
143 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53, 0xFFFFFFFE); in imx_gpc_init()
144 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53, 0xFFFFFFFE); in imx_gpc_init()
145 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53, 0xFFFFFFFE); in imx_gpc_init()
148 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
152 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
155 mmio_setbits_32(IMX_GPC_BASE + LPCR_M4, DSM_MODE_MASK); in imx_gpc_init()
158 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd); in imx_gpc_init()
161 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init()
165 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | in imx_gpc_init()
169 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK); in imx_gpc_init()
180 mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf); in imx_gpc_init()