Lines Matching refs:val
79 uint32_t val; in imx_set_cluster_powerdown() local
82 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_set_cluster_powerdown()
83 val |= A53_LPM_STOP; /* enable C0-C1's STOP mode */ in imx_set_cluster_powerdown()
84 val &= ~CPU_CLOCK_ON_LPM; /* disable CPU clock in LPM mode */ in imx_set_cluster_powerdown()
85 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_set_cluster_powerdown()
91 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
92 val &= ~EN_L2_WFI_PDN; in imx_set_cluster_powerdown()
93 val |= L2PGE | EN_PLAT_PDN; in imx_set_cluster_powerdown()
94 val &= ~COREx_IRQ_WUP(last_core); /* disable IRQ PUP for last core */ in imx_set_cluster_powerdown()
95 val |= COREx_LPM_PUP(last_core); /* enable LPM PUP for last core */ in imx_set_cluster_powerdown()
96 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
109 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_set_cluster_powerdown()
110 val &= ~A53_LPM_MASK; /* clear the C0~1 LPM */ in imx_set_cluster_powerdown()
111 val |= CPU_CLOCK_ON_LPM; /* disable cpu clock in LPM */ in imx_set_cluster_powerdown()
112 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_set_cluster_powerdown()
118 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
119 val |= EN_L2_WFI_PDN; in imx_set_cluster_powerdown()
120 val &= ~(L2PGE | EN_PLAT_PDN); in imx_set_cluster_powerdown()
121 val &= ~COREx_LPM_PUP(last_core); /* disable C0's LPM PUP */ in imx_set_cluster_powerdown()
122 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
128 uint32_t val; in imx_gpc_init() local
148 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
149 val |= IRQ_SRC_A53_WUP; in imx_gpc_init()
151 val &= ~MASTER0_LPM_HSK; in imx_gpc_init()
152 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()