Lines Matching refs:x0
40 mrs x0, mpidr_el1
52 and x1, x0, #MPIDR_CPU_MASK
53 and x0, x0, #MPIDR_CLUSTER_MASK
54 add x0, x1, x0, LSR #7
71 mul x1, x0, x1
75 mov_imm x0, PLAT_MARVELL_UART_BASE
110 mov_imm x0, PLAT_MARVELL_UART_BASE
132 mrs x0, sctlr_el3
133 bic x0, x0, 0x1 /* M bit - MMU */
134 bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */
135 msr sctlr_el3, x0
158 mrs x0, sctlr_el3
159 bic x0, x0, 0x1000 /* I bit - Icache L1 & L2 */
160 msr sctlr_el3, x0
180 ldr x0, =CCU_SRAM_WIN_CR
181 str wzr, [x0]
197 ldr x0, =MASTER_LLC_INV_WAY
198 str w1, [x0]
201 ldr x0, =MASTER_LLC_CTRL
202 str wzr, [x0]
217 mov x28, x0
226 adr x0, __RW_START__
228 sub x1, x1, x0
245 mov x0, x28
246 br x0
254 mrs x0, CORTEX_A72_L2ACTLR_EL1
255 orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
256 msr CORTEX_A72_L2ACTLR_EL1, x0