Lines Matching refs:mmio_read_32
77 mask->mask1 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
79 mask->mask2 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
81 mask->mask3 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
83 mask->mask4 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
85 mask->mask5 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
87 mask->mask6 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
89 mask->mask7 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
91 mask->mask8 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
93 mask->mask9 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
95 mask->mask10 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
97 mask->mask11 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
99 mask->mask12 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
151 return mmio_read_32(base + reg * 4U); in mt_irq_get_pol()
165 config = mmio_read_32(MT_GIC_BASE + GICD_ICFGR + (irq / 16U) * 4U); in mt_irq_get_sens()
304 st = mmio_read_32(addr); in mt_irq_get_en()
399 LSB_vec = mmio_read_32(base + GICD_ISPENDR + in mt_irq_get_pending_vec()
401 MSB_vec = mmio_read_32(base + GICD_ISPENDR + in mt_irq_get_pending_vec()
405 pending_vec = mmio_read_32(base + GICD_ISPENDR + reg * 4); in mt_irq_get_pending_vec()
413 return mmio_read_32((i * 4U) + CIRQ_MASK_BASE); in mt_cirq_get_mask_vec()
455 st = mmio_read_32(CIRQ_CON); in mt_cirq_enable()
471 st = mmio_read_32(CIRQ_CON); in mt_cirq_disable()
510 reg->pending = mmio_read_32(CIRQ_STA_BASE + in cirq_fast_sw_flush()
546 st = mmio_read_32(CIRQ_CON); in mt_cirq_sw_reset()