Lines Matching refs:uint32_t
14 uint32_t mp0_ca7l_cache_config; /* 0x0 */
16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
19 uint32_t mp0_cache_mem_delsel0; /* 0x24 */
20 uint32_t mp0_cache_mem_delsel1; /* 0x28 */
21 uint32_t mp0_axi_config; /* 0x2C */
22 uint32_t mp0_misc_config[10]; /* 0x30 */
23 uint32_t mp0_ca7l_cfg_dis; /* 0x58 */
24 uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */
25 uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */
26 uint32_t mp0_ca7l_misc_config; /* 0x64 */
27 uint32_t mp0_ca7l_dbg_pwr_ctrl; /* 0x68 */
28 uint32_t mp0_rw_rsvd0; /* 0x6C */
29 uint32_t mp0_rw_rsvd1; /* 0x70 */
30 uint32_t mp0_ro_rsvd; /* 0x74 */
31 uint32_t reserved0_0; /* 0x78 */
32 uint32_t mp0_l2_cache_parity1_rdata; /* 0x7C */
33 uint32_t mp0_l2_cache_parity2_rdata; /* 0x80 */
34 uint32_t reserved0_1; /* 0x84 */
35 uint32_t mp0_rgu_dcm_config; /* 0x88 */
36 uint32_t mp0_ca53_specific_ctrl; /* 0x8C */
37 uint32_t mp0_esr_case; /* 0x90 */
38 uint32_t mp0_esr_mask; /* 0x94 */
39 uint32_t mp0_esr_trig_en; /* 0x98 */
40 uint32_t reserved_0_2; /* 0x9C */
41 uint32_t mp0_ses_cg_en; /* 0xA0 */
42 uint32_t reserved0_3[216]; /* 0xA4 */
43 uint32_t mp_dbg_ctrl; /* 0x404 */
44 uint32_t reserved0_4[34]; /* 0x408 */
45 uint32_t mp_dfd_ctrl; /* 0x490 */
46 uint32_t dfd_cnt_l; /* 0x494 */
47 uint32_t dfd_cnt_h; /* 0x498 */
48 uint32_t misccfg_ro_rsvd; /* 0x49C */
49 uint32_t reserved0_5[24]; /* 0x4A0 */
50 uint32_t mp1_rst_status; /* 0x500 */
51 uint32_t mp1_dbg_ctrl; /* 0x504 */
52 uint32_t mp1_dbg_flag; /* 0x508 */
53 uint32_t mp1_ca7l_ir_mon; /* 0x50C */
54 uint32_t reserved0_6[32]; /* 0x510 */
55 uint32_t mcusys_dbg_mon_sel_a; /* 0x590 */
56 uint32_t mcucys_dbg_mon; /* 0x594 */
57 uint32_t misccfg_sec_voi_status0; /* 0x598 */
58 uint32_t misccfg_sec_vio_status1; /* 0x59C */
59 uint32_t reserved0_7[18]; /* 0x5A0 */
60 uint32_t gic500_int_mask; /* 0x5E8 */
61 uint32_t core_rst_en_latch; /* 0x5EC */
62 uint32_t reserved0_8[3]; /* 0x5F0 */
63 uint32_t dbg_core_ret; /* 0x5FC */
64 uint32_t mcusys_config_a; /* 0x600 */
65 uint32_t mcusys_config1_a; /* 0x604 */
66 uint32_t mcusys_gic_prebase_a; /* 0x608 */
67 uint32_t mcusys_pinmux; /* 0x60C */
68 uint32_t sec_range0_start; /* 0x610 */
69 uint32_t sec_range0_end; /* 0x614 */
70 uint32_t sec_range_enable; /* 0x618 */
71 uint32_t l2c_mm_base; /* 0x61C */
72 uint32_t reserved0_9[8]; /* 0x620 */
73 uint32_t aclken_div; /* 0x640 */
74 uint32_t pclken_div; /* 0x644 */
75 uint32_t l2c_sram_ctrl; /* 0x648 */
76 uint32_t armpll_jit_ctrl; /* 0x64C */
77 uint32_t cci_addrmap; /* 0x650 */
78 uint32_t cci_config; /* 0x654 */
79 uint32_t cci_periphbase; /* 0x658 */
80 uint32_t cci_nevntcntovfl; /* 0x65C */
81 uint32_t cci_clk_ctrl; /* 0x660 */
82 uint32_t cci_acel_s1_ctrl; /* 0x664 */
83 uint32_t mcusys_bus_fabric_dcm_ctrl; /* 0x668 */
84 uint32_t mcu_misc_dcm_ctrl; /* 0x66C */
85 uint32_t xgpt_ctl; /* 0x670 */
86 uint32_t xgpt_idx; /* 0x674 */
87 uint32_t reserved0_10[3]; /* 0x678 */
88 uint32_t mcusys_rw_rsvd0; /* 0x684 */
89 uint32_t mcusys_rw_rsvd1; /* 0x688 */
90 uint32_t reserved0_11[13]; /* 0x68C */
91 uint32_t gic_500_delsel_ctl; /* 0x6C0 */
92 uint32_t etb_delsel_ctl; /* 0x6C4 */
93 uint32_t etb_rst_ctl; /* 0x6C8 */
94 uint32_t reserved0_12[29]; /* 0x6CC */
95 uint32_t cci_adb400_dcm_config; /* 0x740 */
96 uint32_t sync_dcm_config; /* 0x744 */
97 uint32_t reserved0_13; /* 0x748 */
98 uint32_t sync_dcm_cluster_config; /* 0x74C */
99 uint32_t sw_udi; /* 0x750 */
100 uint32_t reserved0_14; /* 0x754 */
101 uint32_t gic_sync_dcm; /* 0x758 */
102 uint32_t big_dbg_pwr_ctrl; /* 0x75C */
103 uint32_t gic_cpu_periphbase; /* 0x760 */
104 uint32_t axi_cpu_config; /* 0x764 */
105 uint32_t reserved0_15[2]; /* 0x768 */
106 uint32_t mcsib_sys_ctrl1; /* 0x770 */
107 uint32_t mcsib_sys_ctrl2; /* 0x774 */
108 uint32_t mcsib_sys_ctrl3; /* 0x778 */
109 uint32_t mcsib_sys_ctrl4; /* 0x77C */
110 uint32_t mcsib_dbg_ctrl1; /* 0x780 */
111 uint32_t pwrmcu_apb2to1; /* 0x784 */
112 uint32_t mp0_spmc; /* 0x788 */
113 uint32_t reserved0_16; /* 0x78C */
114 uint32_t mp0_spmc_sram_ctl; /* 0x790 */
115 uint32_t reserved0_17; /* 0x794 */
116 uint32_t mp0_sw_rst_wait_cycle; /* 0x798 */
117 uint32_t reserved0_18; /* 0x79C */
118 uint32_t mp0_pll_divider_cfg; /* 0x7A0 */
119 uint32_t reserved0_19; /* 0x7A4 */
120 uint32_t mp2_pll_divider_cfg; /* 0x7A8 */
121 uint32_t reserved0_20[5]; /* 0x7AC */
122 uint32_t bus_pll_divider_cfg; /* 0x7C0 */
123 uint32_t reserved0_21[7]; /* 0x7C4 */
124 uint32_t clusterid_aff1; /* 0x7E0 */
125 uint32_t clusterid_aff2; /* 0x7E4 */
126 uint32_t reserved0_22[2]; /* 0x7E8 */
127 uint32_t l2_cfg_mp0; /* 0x7F0 */
128 uint32_t l2_cfg_mp1; /* 0x7F4 */
129 uint32_t reserved0_23[218]; /* 0x7F8 */
130 uint32_t mscib_dcm_en; /* 0xB60 */
131 uint32_t reserved0_24[1063]; /* 0xB64 */
132 uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */
133 uint32_t cpusys0_sparken; /* 0x1C04 */
134 uint32_t cpusys0_amuxsel; /* 0x1C08 */
135 uint32_t reserved0_25[9]; /* 0x1C0C */
136 uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */
137 uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */
138 uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */
139 uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */
140 uint32_t reserved0_26[8]; /* 0x1C40 */
141 uint32_t mp0_sync_dcm_cgavg_ctrl; /* 0x1C60 */
142 uint32_t mp0_sync_dcm_cgavg_fact; /* 0x1C64 */
143 uint32_t mp0_sync_dcm_cgavg_rfact; /* 0x1C68 */
144 uint32_t mp0_sync_dcm_cgavg; /* 0x1C6C */
145 uint32_t mp0_l2_parity_clr; /* 0x1C70 */
146 uint32_t reserved0_27[357]; /* 0x1C74 */
147 uint32_t mp2_cpucfg; /* 0x2208 */
148 uint32_t mp2_axi_config; /* 0x220C */
149 uint32_t reserved0_28[25]; /* 0x2210 */
150 uint32_t mp2_sync_dcm; /* 0x2274 */
151 uint32_t reserved0_29[10]; /* 0x2278 */
152 uint32_t ptp3_cputop_spmc0; /* 0x22A0 */
153 uint32_t ptp3_cputop_spmc1; /* 0x22A4 */
154 uint32_t reserved0_30[98]; /* 0x22A8 */
155 uint32_t ptp3_cpu0_spmc0; /* 0x2430 */
156 uint32_t ptp3_cpu0_spmc1; /* 0x2434 */
157 uint32_t ptp3_cpu1_spmc0; /* 0x2438 */
158 uint32_t ptp3_cpu1_spmc1; /* 0x243C */
159 uint32_t ptp3_cpu2_spmc0; /* 0x2440 */
160 uint32_t ptp3_cpu2_spmc1; /* 0x2444 */
161 uint32_t ptp3_cpu3_spmc0; /* 0x2448 */
162 uint32_t ptp3_cpu3_spmc1; /* 0x244C */
163 uint32_t ptp3_cpux_spmc; /* 0x2450 */
164 uint32_t reserved0_31[171]; /* 0x2454 */
165 uint32_t spark2ld0; /* 0x2700 */