Lines Matching refs:BIT
11 #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
12 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
13 BIT(16) | \
14 BIT(17) | \
15 BIT(18) | \
16 BIT(21))
17 #define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
18 BIT(16) | \
19 BIT(17) | \
20 BIT(18))
21 #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
22 #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
23 BIT(16) | \
24 BIT(17) | \
25 BIT(18) | \
26 BIT(21))
27 #define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
28 BIT(16) | \
29 BIT(17) | \
30 BIT(18))
86 #define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
87 #define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
88 #define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
89 #define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
90 #define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
91 #define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
140 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11))
141 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11))
170 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
171 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
230 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11))
231 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11))
260 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11))
261 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11))
290 #define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK (BIT(11))
291 #define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON (BIT(11))
320 #define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK (BIT(11))
321 #define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON (BIT(11))
350 #define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK (BIT(11))
351 #define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON (BIT(11))
380 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
381 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
440 #define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
441 BIT(4))
442 #define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
443 BIT(4))
473 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
474 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
475 BIT(1) | \
476 BIT(2) | \
477 BIT(3))
478 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
479 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
480 BIT(1) | \
481 BIT(2) | \
482 BIT(3))
524 #define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
525 BIT(1) | \
526 BIT(2) | \
527 BIT(3))
528 #define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
529 BIT(1) | \
530 BIT(2) | \
531 BIT(3))