Lines Matching refs:x0
64 mrs x0, midr_el1
66 and x0, x0, x1
67 lsr x0, x0, #MIDR_PN_SHIFT
68 cmp x0, #MIDR_PN_CORTEX_A57
75 mrs x0, CORTEX_A57_L2ECTLR_EL1
77 bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
78 orr x0, x0, x1
79 msr CORTEX_A57_L2ECTLR_EL1, x0
82 mrs x0, CORTEX_A57_ECTLR_EL1
84 bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
85 orr x0, x0, x1
86 msr CORTEX_A57_ECTLR_EL1, x0
93 mrs x0, actlr_el3
95 orr x0, x0, x1
96 msr actlr_el3, x0
97 mrs x0, actlr_el2
99 orr x0, x0, x1
100 msr actlr_el2, x0
107 1: mrs x0, pmcr_el0
108 ubfx x0, x0, #11, #5 // read PMCR.N field
110 lsl x0, x1, x0
111 sub x0, x0, #1 // mask of event counters
112 orr x0, x0, #0x80000000 // disable overflow intrs
113 msr pmintenclr_el1, x0
122 mrs x0, cntkctl_el1
123 orr x0, x0, #EL0VCTEN_BIT
124 msr cntkctl_el1, x0
134 mrs x0, mpidr_el1
135 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
136 cmp x0, #TEGRA_PRIMARY_CPU
137 cset x0, eq
150 mrs x0, mpidr_el1
166 ldr x0, [x1]
179 mov x0, #0
191 mov x0, #0
216 mov x0, x17
224 stp x3, x4, [x0], #16
231 strb w3, [x0], #1
239 _end: mov x0, x20
272 lsr x1, x0, #MPIDR_AFF0_SHIFT
274 lsr x2, x0, #MPIDR_AFF1_SHIFT
278 mov x0, #-1
289 add x0, x1, x3
307 mov x0, #TEGRA_MISC_BASE
308 add x0, x0, #HARDWARE_REVISION_OFFSET
309 ldr w1, [x0]
314 ldr w1, [x0]
325 mrs x0, CORTEX_A57_CPUACTLR_EL1
326 orr x0, x0, #1
327 msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
334 mrs x0, CORTEX_A57_CPUACTLR_EL1
335 bic x0, x0, #1
351 mrs x0, oslsr_el1
352 and x0, x0, #2
354 bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */
356 mov x0, xzr
357 msr oslar_el1, x0 /* os lock stays 0 across warm reset */
388 mov x0, #1
389 msr oslar_el1, x0
396 br x0