Lines Matching refs:x1
82 mov x1, xzr
135 ldr x1, =NXP_DCFG_ADDR
138 ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
182 ldr x1, =NXP_SEC_REGFILE_ADDR
183 str w0, [x1, #CORE_HOLD_OFFSET]
186 mov x1, #NXP_RESET_ADDR
187 ldr w2, [x1, #BRR_OFFSET]
189 str w2, [x1, #BRR_OFFSET]
210 mov x1, x0
214 lsr x1, x0, #32
255 and x1, x0, #MPIDR_AFFINITY0_MASK
257 lsl x2, x2, x1
260 and x1, x0, #MPIDR_AFFINITY1_MASK
261 lsl x1, x1, #8
262 orr x2, x2, x1
293 mrs x1, CPUECTLR_EL1
296 orr x1, x1, #CPUECTLR_SMPEN_EN
297 orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
298 bic x1, x1, #CPUECTLR_INS_PREFETCH_MASK
299 bic x1, x1, #CPUECTLR_DAT_PREFETCH_MASK
302 bic x1, x1, #CPUECTLR_TIMER_MASK
303 orr x1, x1, #CPUECTLR_TIMER_2TICKS
304 msr CPUECTLR_EL1, x1
394 mov x1, #CNTP_CTL_EL0_EN
395 orr x1, x1, #CNTP_CTL_EL0_IMASK
396 msr cntp_ctl_el0, x1
561 mov x1, #SCTLR_I_C_M_MASK
563 bic x0, x0, x1
613 mrs x1, spsr_el1
614 orr x1, x1, x2
615 msr spsr_el1, x1
617 mrs x1, spsr_el2
618 orr x1, x1, x2
619 msr spsr_el2, x1
653 mrs x1, CPUECTLR_EL1
654 bic x1, x1, #CPUECTLR_TIMER_MASK
655 msr CPUECTLR_EL1, x1
707 mrs x1, CPUECTLR_EL1
708 bic x1, x1, #CPUECTLR_RET_MASK
709 orr x1, x1, #CPUECTLR_TIMER_2TICKS
710 orr x1, x1, #CPUECTLR_SMPEN_EN
711 msr CPUECTLR_EL1, x1
753 mrs x1, CPUECTLR_EL1
754 bic x1, x1, #CPUECTLR_TIMER_MASK
755 msr CPUECTLR_EL1, x1
791 mrs x1, CPUECTLR_EL1
792 bic x1, x1, #CPUECTLR_RET_MASK
793 orr x1, x1, #CPUECTLR_TIMER_2TICKS
794 orr x1, x1, #CPUECTLR_SMPEN_EN
795 msr CPUECTLR_EL1, x1
821 mrs x1, CPUECTLR_EL1
822 bic x1, x1, #CPUECTLR_TIMER_MASK
823 msr CPUECTLR_EL1, x1
909 ldr x1, =GICD_IROUTER76_OFFSET
911 ldr w5, [x2, x1]
913 ldr x1, =GICD_IROUTER113_OFFSET
915 ldr w7, [x2, x1]
929 str w4, [x2, x1]
931 ldr x1, =GICD_IROUTER76_OFFSET
933 str w4, [x2, x1]
1112 ldr x1, =GICD_IROUTER113_OFFSET
1113 str w2, [x3, x1]
1114 ldr x1, =GICD_IROUTER112_OFFSET
1115 str w0, [x3, x1]
1117 ldr x1, =GICD_IROUTER76_OFFSET
1118 str w2, [x3, x1]
1119 ldr x1, =GICD_IROUTER60_OFFSET
1120 str w0, [x3, x1]
1127 ldp x2, x1, [sp], #16
1146 mrs x1, SCTLR_EL1
1147 orr x1, x1, #0x4
1148 msr SCTLR_EL1, x1
1151 mrs x1, osdlr_el1
1152 bic x1, x1, #OSDLR_EL1_DLK_LOCK
1153 msr osdlr_el1, x1
1156 mrs x1, SCTLR_EL3
1157 orr x1, x1, #SCTLR_I_MASK
1158 msr SCTLR_EL3, x1
1171 ldr x1, =TZPCDECPROT_0_SET_BASE /* decode Protection-0 Set Reg */
1173 str w0, [x1]
1175 ldr x1, =TZPCDECPROT_1_SET_BASE /* decode Protection-1 Set Reg */
1177 str w0, [x1]
1179 ldr x1, =TZPCDECPROT_2_SET_BASE /* decode Protection-2 Set Reg */
1181 str w0, [x1]
1184 ldr x1, =NXP_OCRAM_TZPC_ADDR /* secure RAM region size Reg */
1186 str w0, [x1]
1196 ldr x1, =NXP_SNVS_ADDR
1197 ldr w0, [x1, #SECMON_HPCOMR_OFFSET]
1201 str w0, [x1, #SECMON_HPCOMR_OFFSET]
1256 mov x1, #CORE_DISABLED
1333 mov x1, #GIC_RD_OFFSET
1336 add x0, x0, x1
1358 mov x1, #GIC_SGI_OFFSET
1361 add x0, x0, x1
1385 ldr x1, =NXP_RESET_ADDR
1386 ldr w0, [x1, x0]