Lines Matching refs:x3
151 mov x3, x30
163 mov x30, x3
176 mov x3, x30
197 mov x30, x3
366 mrs x3, osdlr_el1
367 orr x3, x3, #OSDLR_EL1_DLK_LOCK
368 msr osdlr_el1, x3
372 mov x3, #ICC_IGRPEN0_EL1_EN
373 msr ICC_IGRPEN0_EL1, x3
386 ldr x3, =NXP_TIMER_ADDR
387 ldr w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
391 str w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
421 mov x3, #ICC_IAR0_EL1_SGI15
422 cmp x2, x3
485 mrs x3, osdlr_el1
486 bic x3, x3, #OSDLR_EL1_DLK_LOCK
487 msr osdlr_el1, x3
502 mov x3, x30
583 mov x3, #NXP_PMU_ADDR
585 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
590 mov x3, #NXP_PMU_ADDR
591 str w0, [x3, #PMU_CLAINACTSETR_OFFSET]
594 mov x3, #NXP_PMU_ADDR
596 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
601 mov x3, #NXP_PMU_ADDR
602 str w0, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
604 ldr w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
608 str w0, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
610 str w0, [x3, #PMU_CLSINACTSETR_OFFSET]
636 str w1, [x3, x0]
872 mov x3, #NXP_PMU_ADDR
970 mov x3, #NXP_PMU_ADDR
972 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
980 mov x3, #NXP_PMU_ADDR
982 str w0, [x3, #PMU_CLAINACTSETR_OFFSET]
986 mov x3, #NXP_PMU_ADDR
988 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
994 mov x3, #NXP_PMU_ADDR
996 str w0, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
1000 ldr w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
1006 str w0, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
1008 str w0, [x3, #PMU_CLSINACTSETR_OFFSET]
1021 mov x3, #0x1
1022 lsl x3, x3, x0
1024 mov x0, x3
1034 lsr x3, x3, #1
1035 cbnz x3, 2b
1043 mov x3, #NXP_PMU_ADDR
1046 str w1, [x3, x0]
1058 mov x3, NXP_PMU_ADDR
1061 str w0, [x3, #PMU_CLAINACTCLRR_OFFSET]
1062 str w0, [x3, #PMU_CLSINACTCLRR_OFFSET]
1066 ldr w1, [x3, #PMU_CLAINACTSETR_OFFSET]
1069 ldr w1, [x3, #PMU_CLSINACTSETR_OFFSET]
1078 mov x3, #0x1
1079 lsl x3, x3, x0
1081 mov x0, x3
1090 lsr x3, x3, #1
1091 cbnz x3, 2b
1099 ldr x3, =NXP_EPU_ADDR
1110 ldr x3, =NXP_GICD_ADDR
1113 str w2, [x3, x1]
1115 str w0, [x3, x1]
1118 str w2, [x3, x1]
1120 str w0, [x3, x1]
1123 ldr x3, =NXP_EPU_ADDR
1125 str w2, [x3, #EPU_EPGCR_OFFSET]
1126 str w0, [x3, #EPU_EPCTR10_OFFSET]
1128 str w1, [x3, #EPU_EPCCR10_OFFSET]
1129 str w2, [x3, #EPU_EPIMCR10_OFFSET]