Lines Matching refs:str
191 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
195 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
212 str w0, [x1, #CORE_HOLD_OFFSET]
220 str w2, [x1, #BRR_OFFSET]
269 str w2, [x5, #GICD_CTLR_OFFSET]
357 str w3, [x5, #GICR_ICENABLER0_OFFSET]
375 str w4, [x5, #GICR_IGROUPR0_OFFSET]
380 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
385 str w4, [x5, #GICR_IPRIORITYR3_OFFSET]
389 str w3, [x5, #GICR_ISENABLER0_OFFSET]
415 str w1, [x5, #GICR_ICPENDR0_OFFSET]
423 str w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
499 str w1, [x4, #GICR_ICENABLER0_OFFSET]
537 str w0, [x2, #RSTCNTL_OFFSET]
541 str w0, [x2, #RSTCNTL_OFFSET]
572 str w1, [x0, #RST_RSTRQMR1_OFFSET]
578 str w1, [x2, x0]
581 str w1, [x2, x0]
584 str w1, [x2, x0]
589 str w1, [x0]
608 str x0, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
622 str w1, [x3, #PMU_CLAINACTSETR_OFFSET]
630 str w1, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
638 str w1, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
641 str w1, [x3, #PMU_CLSINACTSETR_OFFSET]
667 str w1, [x3, x0]
734 str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
824 str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
921 str x7, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
936 str w4, [x2, x3]
1010 str w7, [x1, x15]
1019 str w8, [x1, x16]
1026 str w9, [x1, x17]
1033 str w10, [x1, x18]
1054 str w11, [x1, x19]
1061 str w12, [x1, x20]
1166 str w7, [x3, #DCFG_DEVDISR1_OFFSET]
1169 str w8, [x3, #DCFG_DEVDISR2_OFFSET]
1172 str w9, [x3, #DCFG_DEVDISR3_OFFSET]
1175 str w10, [x3, #DCFG_DEVDISR4_OFFSET]
1178 str w11, [x3, #DCFG_DEVDISR5_OFFSET]
1181 str w12, [x3, #DCFG_DEVDISR6_OFFSET]
1236 str w18, [x3, #DCFG_DEVDISR6_OFFSET]
1237 str w17, [x3, #DCFG_DEVDISR5_OFFSET]
1238 str w16, [x3, #DCFG_DEVDISR4_OFFSET]
1239 str w15, [x3, #DCFG_DEVDISR3_OFFSET]
1240 str w14, [x3, #DCFG_DEVDISR2_OFFSET]
1241 str w13, [x3, #DCFG_DEVDISR1_OFFSET]
1251 str w14, [x1, x15]
1253 str w13, [x1, x16]
1255 str w12, [x1, x17]
1257 str w11, [x1, x18]
1259 str w10, [x1, x19]
1261 str w9, [x1, x20]
1328 str w9, [x2, x8]
1342 str x7, [x9, #CCN_HN_F_SNP_DMN_CTL_SET_OFFSET]
1408 str w8, [x4, #DDR_CFG_2_OFFSET]
1413 str w8, [x5, #DDR_CFG_2_OFFSET]
1419 str w9, [x1, x16]
1438 str w9, [x3, #DCFG_DEVDISR5_OFFSET]
1442 str w8, [x1, x12]
1446 str w9, [x1, x13]
1463 str w9, [x1, x15]
1467 str w8, [x1, x14]
1471 str w7, [x3, #DCFG_DEVDISR5_OFFSET]
1473 str w6, [x1, x16]
1494 str w9, [x5, #DDR_CFG_2_OFFSET]
1499 str w9, [x4, #DDR_CFG_2_OFFSET]
1639 str w1, [x0, #DCFG_COREDISR_OFFSET]
1643 str w2, [x0, #DCFG_COREDISABLEDSR_OFFSET]
1674 str w0, [x1]
1680 str w0, [x1]
1686 str w0, [x1]
1693 str w0, [x1]
1705 str w1, [x2, x0]
1810 str w1, [x2, x0]