Lines Matching refs:x1
102 mov x1, xzr
190 mov x1, x0
194 lsr x1, x0, #32
207 ldr x1, =NXP_SEC_REGFILE_ADDR
212 str w0, [x1, #CORE_HOLD_OFFSET]
215 mov x1, #NXP_RESET_ADDR
216 ldr w2, [x1, #BRR_OFFSET]
220 str w2, [x1, #BRR_OFFSET]
242 ldr x1, =NXP_DCFG_ADDR
245 ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
291 and x1, x0, #MPIDR_AFFINITY0_MASK
293 lsl x2, x2, x1
296 and x1, x0, #MPIDR_AFFINITY1_MASK
297 lsl x1, x1, #8
298 orr x2, x2, x1
327 mrs x1, CORTEX_A72_ECTLR_EL1
330 orr x1, x1, #CPUECTLR_SMPEN_EN
331 orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
332 bic x1, x1, #CPUECTLR_INS_PREFETCH_MASK
333 bic x1, x1, #CPUECTLR_DAT_PREFETCH_MASK
336 bic x1, x1, #CPUECTLR_TIMER_MASK
337 orr x1, x1, #CPUECTLR_TIMER_8TICKS
338 msr CORTEX_A72_ECTLR_EL1, x1
426 mov x1, #CNTP_CTL_EL0_EN
427 orr x1, x1, #CNTP_CTL_EL0_IMASK
428 msr cntp_ctl_el0, x1
592 mov x1, #SCTLR_I_C_M_MASK
594 bic x0, x0, x1
599 bic x1, x1, #CPUECTLR_TIMER_MASK
606 mov x1, #NXP_CCN_HN_F_0_ADDR
608 str x0, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
610 ldr w2, [x1, #CCN_HN_F_SNP_DMN_CTL_OFFSET]
644 mrs x1, spsr_el1
645 orr x1, x1, x2
646 msr spsr_el1, x1
648 mrs x1, spsr_el2
649 orr x1, x1, x2
650 msr spsr_el2, x1
700 mrs x1, CORTEX_A72_ECTLR_EL1
701 bic x1, x1, #CPUECTLR_TIMER_MASK
702 msr CORTEX_A72_ECTLR_EL1, x1
740 mrs x1, CORTEX_A72_ECTLR_EL1
741 bic x1, x1, #CPUECTLR_RET_MASK
742 orr x1, x1, #CPUECTLR_TIMER_8TICKS
743 orr x1, x1, #CPUECTLR_SMPEN_EN
744 msr CORTEX_A72_ECTLR_EL1, x1
790 mrs x1, CORTEX_A72_ECTLR_EL1
791 bic x1, x1, #CPUECTLR_TIMER_MASK
792 msr CORTEX_A72_ECTLR_EL1, x1
830 mrs x1, CORTEX_A72_ECTLR_EL1
831 bic x1, x1, #CPUECTLR_RET_MASK
832 orr x1, x1, #CPUECTLR_TIMER_8TICKS
833 orr x1, x1, #CPUECTLR_SMPEN_EN
834 msr CORTEX_A72_ECTLR_EL1, x1
862 mrs x1, CORTEX_A72_ECTLR_EL1
863 bic x1, x1, #CPUECTLR_TIMER_MASK
864 msr CORTEX_A72_ECTLR_EL1, x1
890 mrs x1, CORTEX_A72_ECTLR_EL1
892 orr x1, x1, #CPUECTLR_SMPEN_MASK
894 orr x1, x1, #CPUECTLR_RET_8CLK
896 orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
897 msr CORTEX_A72_ECTLR_EL1, x1
917 ldr x1, =NXP_CCN_HN_F_0_ADDR
918 ldr x7, [x1, #CCN_HN_F_SNP_DMN_CTL_OFFSET]
921 str x7, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
923 add x1, x1, #CCN_HNF_OFFSET
930 ldr x1, =NXP_PMU_CCSR_ADDR
975 ldr w9, [x1, x15]
977 ldr w10, [x1, x16]
979 ldr w11, [x1, x17]
981 ldr w12, [x1, x18]
983 ldr w13, [x1, x19]
985 ldr w14, [x1, x20]
1006 ldr w4, [x1, x21]
1010 str w7, [x1, x15]
1017 ldr w6, [x1, x21]
1019 str w8, [x1, x16]
1024 ldr w4, [x1, x21]
1026 str w9, [x1, x17]
1031 ldr w6, [x1, x21]
1033 str w10, [x1, x18]
1052 ldr w4, [x1, x21]
1054 str w11, [x1, x19]
1059 ldr w6, [x1, x21]
1061 str w12, [x1, x20]
1078 ldr w5, [x1, x21]
1089 ldr w5, [x1, x21]
1100 ldr w5, [x1, x21]
1111 ldr w5, [x1, x21]
1122 ldr w5, [x1, x21]
1133 ldr w5, [x1, x21]
1251 str w14, [x1, x15]
1253 str w13, [x1, x16]
1255 str w12, [x1, x17]
1257 str w11, [x1, x18]
1259 str w10, [x1, x19]
1261 str w9, [x1, x20]
1268 ldr w5, [x1, x15]
1278 ldr w5, [x1, x15]
1288 ldr w5, [x1, x15]
1298 ldr w5, [x1, x15]
1308 ldr w5, [x1, x15]
1318 ldr w5, [x1, x15]
1361 mrs x1, CORTEX_A72_ECTLR_EL1
1363 orr x1, x1, #CPUECTLR_SMPEN_MASK
1366 bic x1, x1, x2
1369 bic x1, x1, x2
1370 msr CORTEX_A72_ECTLR_EL1, x1
1419 str w9, [x1, x16]
1431 ldr w8, [x1, x17]
1442 str w8, [x1, x12]
1446 str w9, [x1, x13]
1463 str w9, [x1, x15]
1467 str w8, [x1, x14]
1473 str w6, [x1, x16]
1486 ldr w8, [x1, x17]
1527 mov x1, #NXP_DCFG_ADDR
1528 ldr w2, [x1, #RCW_SR27_OFFSET]
1598 mov x1, #CORE_STATE_DATA
1614 mov x1, #CORE_STATE_DATA
1671 ldr x1, =TZPCDECPROT_0_SET_BASE
1674 str w0, [x1]
1677 ldr x1, =TZPCDECPROT_1_SET_BASE
1680 str w0, [x1]
1683 ldr x1, =TZPCDECPROT_2_SET_BASE
1686 str w0, [x1]
1690 ldr x1, =TZPC_BASE
1693 str w0, [x1]
1763 mov x1, #GIC_RD_OFFSET
1770 add x0, x0, x1
1791 mov x1, #GIC_SGI_OFFSET
1796 add x0, x0, x1
1821 ldr x1, =NXP_RESET_ADDR
1822 ldr w0, [x1, x0]