Lines Matching refs:x3
205 mov x3, x30
228 mov x30, x3
399 mrs x3, osdlr_el1
400 orr x3, x3, #OSDLR_EL1_DLK_LOCK
401 msr osdlr_el1, x3
405 mov x3, #ICC_IGRPEN0_EL1_EN
406 msr ICC_IGRPEN0_EL1, x3
418 ldr x3, =NXP_TIMER_ADDR
419 ldr w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
423 str w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
452 mov x3, #ICC_IAR0_EL1_SGI15
453 cmp x2, x3
513 mrs x3, osdlr_el1
514 bic x3, x3, #OSDLR_EL1_DLK_LOCK
515 msr osdlr_el1, x3
614 mov x3, #NXP_PMU_ADDR
617 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
622 str w1, [x3, #PMU_CLAINACTSETR_OFFSET]
625 ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
630 str w1, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
633 ldr w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
638 str w1, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
641 str w1, [x3, #PMU_CLSINACTSETR_OFFSET]
667 str w1, [x3, x0]
934 mov x3, #PMU_POWMGTDCR0_OFFSET
936 str w4, [x2, x3]
1003 ldr x3, =DEVDISR1_MASK
1022 ldr x3, =DEVDISR3_MASK
1042 ldr x3, =DEVDISR5_MASK
1151 mov x3, #NXP_DCFG_ADDR
1154 ldr w13, [x3, #DCFG_DEVDISR1_OFFSET]
1155 ldr w14, [x3, #DCFG_DEVDISR2_OFFSET]
1156 ldr w15, [x3, #DCFG_DEVDISR3_OFFSET]
1157 ldr w16, [x3, #DCFG_DEVDISR4_OFFSET]
1158 ldr w17, [x3, #DCFG_DEVDISR5_OFFSET]
1159 ldr w18, [x3, #DCFG_DEVDISR6_OFFSET]
1166 str w7, [x3, #DCFG_DEVDISR1_OFFSET]
1169 str w8, [x3, #DCFG_DEVDISR2_OFFSET]
1172 str w9, [x3, #DCFG_DEVDISR3_OFFSET]
1175 str w10, [x3, #DCFG_DEVDISR4_OFFSET]
1178 str w11, [x3, #DCFG_DEVDISR5_OFFSET]
1181 str w12, [x3, #DCFG_DEVDISR6_OFFSET]
1236 str w18, [x3, #DCFG_DEVDISR6_OFFSET]
1237 str w17, [x3, #DCFG_DEVDISR5_OFFSET]
1238 str w16, [x3, #DCFG_DEVDISR4_OFFSET]
1239 str w15, [x3, #DCFG_DEVDISR3_OFFSET]
1240 str w14, [x3, #DCFG_DEVDISR2_OFFSET]
1241 str w13, [x3, #DCFG_DEVDISR1_OFFSET]
1438 str w9, [x3, #DCFG_DEVDISR5_OFFSET]
1471 str w7, [x3, #DCFG_DEVDISR5_OFFSET]
1604 mov x3, #CLUSTER_3_CORES_MASK
1605 tst x3, x7