Lines Matching refs:x1
45 ldr x1, =NXP_DDR_ADDR
47 ldr w0, [x1, #SDRAM_CFG]
49 str w0, [x1, #SDRAM_CFG]
51 ldr w0, [x1, #DEBUG_2]
55 ldr w0, [x1, #DEBUG_26]
64 str w0, [x1, #DEBUG_26]
66 ldr w0, [x1, #SDRAM_CFG_2]
68 str w0, [x1, #SDRAM_CFG_2]
71 ldr w0, [x1, #DDR_DSR2]
73 str w0, [x1, #DDR_DSR2]
74 ldr w0, [x1, #DDR_DSR2]
78 ldr w0, [x1, #SDRAM_INTERVAL]
80 str w0, [x1, #SDRAM_INTERVAL]
84 ldr w0, [x1, #SDRAM_MD_CNTL]
87 str w0, [x1, #SDRAM_MD_CNTL]
89 ldr w0, [x1, #TIMING_CFG_10]
91 str w0, [x1, #TIMING_CFG_10]
93 ldr w0, [x1, #SDRAM_CFG_2]
95 str w0, [x1, #SDRAM_CFG_2]
98 ldr w0, [x1, #DDR_DSR2]
105 ldr w0, [x1, #DEBUG_26]
108 str w0, [x1, #DEBUG_26]
112 ldr x1, =NXP_DDR2_ADDR
126 ldr x1, =NXP_SNVS_ADDR
127 ldr w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
136 str w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
151 ldr x1, =NXP_FLEXSPI_ADDR
152 ldr w0, [x1, #FSPI_IPCMD]
154 str w0, [x1, #FSPI_IPCMD]
156 ldr w0, [x1, #FSPI_INTR]
161 ldr w0, [x1, #FSPI_IPTXFCR]
163 str w0, [x1, #FSPI_IPTXFCR]
165 ldr w0, [x1, #FSPI_INTR]
167 str w0, [x1, #FSPI_INTR]