Lines Matching refs:reg
213 uint32_t reg; in bl2_lossy_setting() local
217 reg = format | (start_addr >> 20); in bl2_lossy_setting()
218 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); in bl2_lossy_setting()
220 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); in bl2_lossy_setting()
240 uint32_t reg; in bl2_plat_flush_bl31_params() local
242 reg = mmio_read_32(RCAR_MODEMR); in bl2_plat_flush_bl31_params()
243 boot_dev = reg & MODEMR_BOOT_DEV_MASK; in bl2_plat_flush_bl31_params()
250 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) { in bl2_plat_flush_bl31_params()
254 reg = mmio_read_32(RCAR_PRR); in bl2_plat_flush_bl31_params()
255 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); in bl2_plat_flush_bl31_params()
256 product = reg & PRR_PRODUCT_MASK; in bl2_plat_flush_bl31_params()
257 cut = reg & PRR_CUT_MASK; in bl2_plat_flush_bl31_params()
265 reg = mmio_read_32(RCAR_MODEMR); in bl2_plat_flush_bl31_params()
266 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; in bl2_plat_flush_bl31_params()
430 uint32_t reg; in bl2_populate_compatible_string() local
466 reg = mmio_read_32(RCAR_PRR); in bl2_populate_compatible_string()
467 switch (reg & PRR_PRODUCT_MASK) { in bl2_populate_compatible_string()
650 uint32_t reg, midr, boot_dev, boot_cpu, type, rev; in bl2_el3_early_platform_setup() local
689 reg = mmio_read_32(RCAR_MODEMR); in bl2_el3_early_platform_setup()
690 boot_dev = reg & MODEMR_BOOT_DEV_MASK; in bl2_el3_early_platform_setup()
691 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; in bl2_el3_early_platform_setup()
710 reg = read_midr(); in bl2_el3_early_platform_setup()
711 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
727 reg = mmio_read_32(RCAR_PRR); in bl2_el3_early_platform_setup()
728 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); in bl2_el3_early_platform_setup()
729 product = reg & PRR_PRODUCT_MASK; in bl2_el3_early_platform_setup()
750 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) { in bl2_el3_early_platform_setup()
751 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) { in bl2_el3_early_platform_setup()
756 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); in bl2_el3_early_platform_setup()
759 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; in bl2_el3_early_platform_setup()
761 minor = reg & RCAR_MINOR_MASK; in bl2_el3_early_platform_setup()
767 reg = mmio_read_32(RCAR_MODEMR); in bl2_el3_early_platform_setup()
768 sscg = reg & RCAR_SSCG_MASK; in bl2_el3_early_platform_setup()
833 reg = rcar_rom_get_lcs(&lcs); in bl2_el3_early_platform_setup()
834 if (reg != 0U) { in bl2_el3_early_platform_setup()
909 reg = mmio_read_32(RST_WDTRSTCR); in bl2_el3_early_platform_setup()
910 reg &= ~WDTRSTCR_RWDT_RSTMSK; in bl2_el3_early_platform_setup()
911 reg |= WDTRSTCR_PASSWORD; in bl2_el3_early_platform_setup()
912 mmio_write_32(RST_WDTRSTCR, reg); in bl2_el3_early_platform_setup()
917 reg = mmio_read_32(RCAR_PRR); in bl2_el3_early_platform_setup()
918 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) { in bl2_el3_early_platform_setup()
923 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) { in bl2_el3_early_platform_setup()
929 reg = mmio_read_32(CPG_PLL2CR); in bl2_el3_early_platform_setup()
930 reg &= ~((uint32_t)1 << 5); in bl2_el3_early_platform_setup()
931 mmio_write_32(CPG_PLL2CR, reg); in bl2_el3_early_platform_setup()
933 reg = mmio_read_32(CPG_PLL4CR); in bl2_el3_early_platform_setup()
934 reg &= ~((uint32_t)1 << 5); in bl2_el3_early_platform_setup()
935 mmio_write_32(CPG_PLL4CR, reg); in bl2_el3_early_platform_setup()
937 reg = mmio_read_32(CPG_PLL0CR); in bl2_el3_early_platform_setup()
938 reg &= ~((uint32_t)1 << 12); in bl2_el3_early_platform_setup()
939 mmio_write_32(CPG_PLL0CR, reg); in bl2_el3_early_platform_setup()