Lines Matching refs:mmio_write_32
63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
98 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
106 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
179 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()
188 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
201 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, CRU_GLB_SRST_FST_VALUE); in rockchip_soc_soft_reset()
223 mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX, val); in rockchip_soc_system_off()
228 mmio_write_32(GPIO2_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off()
256 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_suspend()
266 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_resume()
286 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
289 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
292 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
307 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
309 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
317 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
319 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
321 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
358 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_resume()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
383 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(0), in pm_plls_suspend()
387 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_suspend()
391 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(20), in pm_plls_suspend()
395 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(24), in pm_plls_suspend()
399 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18), in pm_plls_suspend()
403 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), in pm_plls_suspend()
411 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), in pm_plls_resume()
417 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18), in pm_plls_resume()
421 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(24), in pm_plls_resume()
425 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(20), in pm_plls_resume()
429 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_resume()
433 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(0), in pm_plls_resume()
474 mmio_write_32(GRF_BASE + PMIC_SLEEP_REG, BITS_WITH_WMASK(0, 0x3, 4)); in rk3328_pmic_suspend()
475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend()
477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
485 mmio_write_32(GRF_BASE + PMIC_SLEEP_REG, in rk3328_pmic_resume()
500 mmio_write_32(DDR_GRF_BASE, BIT_WITH_WMSK(14) | WMSK_BIT(15)); in ddr_suspend()
517 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in ddr_suspend()
519 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in ddr_suspend()
521 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in ddr_suspend()
523 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in ddr_suspend()
534 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in dmc_restore()
536 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in dmc_restore()
538 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in dmc_restore()
540 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in dmc_restore()
551 mmio_write_32(DDR_GRF_BASE, sram_data.ddr_grf_con0 | 0xc0000000); in dmc_restore()
560 mmio_write_32(UART2_BASE + UART_IER, UART_INT_DISABLE); in sram_dbg_uart_suspend()
561 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20002000); in sram_dbg_uart_suspend()
562 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040004); in sram_dbg_uart_suspend()
568 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20000000); in sram_dbg_uart_resume()
569 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040000); in sram_dbg_uart_resume()
570 mmio_write_32(UART2_BASE + UART_FCR, UART_FIFO_RESET); in sram_dbg_uart_resume()
571 mmio_write_32(UART2_BASE + UART_IER, sram_data.uart2_ier); in sram_dbg_uart_resume()
581 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(PD_CPU0), apm_value); in sram_soc_enter_lp()
602 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in sram_suspend()
659 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in plat_rockchip_pmu_init()