Lines Matching defs:n
15 #define PMUCRU_PPLL_CON(n) ((n) * 4) argument
16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
29 #define FBDIV(n) ((0xfff << 16) | n) argument
30 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) argument
31 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) argument
32 #define REFDIV(n) ((0x3F << 16) | n) argument
33 #define PLL_LOCK(n) ((n >> 31) & 0x1) argument
46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) argument
56 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) argument
57 #define CRU_GATE_CON(n) (0x300 + (n) * 4) argument
147 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) argument
176 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) argument
190 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) argument
198 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) argument
210 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) argument
225 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) argument
226 #define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) argument
227 #define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) argument
228 #define PWM_CTRL(n) (0x000c + 0x10 * (n)) argument
257 #define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4) argument
267 #define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4) argument