Lines Matching refs:write_aux_reg
285 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_enable()
294 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_disable()
389 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_entire_op()
392 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); in __slc_entire_op()
394 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); in __slc_entire_op()
417 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); in slc_upper_region_init()
418 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); in slc_upper_region_init()
450 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_rgn_op()
464 write_aux_reg(ARC_AUX_SLC_RGN_END, end); in __slc_rgn_op()
465 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); in __slc_rgn_op()
506 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, in arc_ioc_setup()
509 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); in arc_ioc_setup()
510 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); in arc_ioc_setup()
511 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); in arc_ioc_setup()
584 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & in icache_enable()
595 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | in icache_disable()
606 write_aux_reg(ARC_AUX_IC_IVIC, 1); in __ic_entire_invalidate()
639 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & in dcache_enable()
659 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | in dcache_disable()
680 write_aux_reg(ARC_AUX_DC_PTAG, paddr); in __dcache_line_loop()
682 write_aux_reg(aux_cmd, paddr); in __dcache_line_loop()
699 write_aux_reg(ARC_AUX_DC_CTRL, ctrl); in __before_dc_op()
722 write_aux_reg(aux, 0x1); in __dc_entire_op()