Lines Matching refs:ldr
25 ldr sp,SRAM_STACK_V
32 ldr r0,DDR_07_V
33 ldr r1,[r0]
34 ldr r2,DDR_ACTIVE_V
37 ldr r0,DDR_57_V
38 ldr r1,[r0]
39 ldr r2,CYCLES_MASK_V
41 ldr r2,REFRESH_CYCLES_V
44 ldr r0,DDR_07_V
45 ldr r1,[r0]
46 ldr r2,SREFRESH_MASK_V
55 ldr r0,SREFRESH_DELAY_V
62 ldr r0,SCCTRL_V
74 ldr r6,PLL2_FREQ_V
75 ldr r7,PLL2_CNTL_V
80 ldr r6,PLL1_FREQ_V
81 ldr r7,PLL1_CNTL_V
85 ldr r1,[r0]
86 ldr r2,PLLFREQ_MASK_V
93 ldr r1,P1C0A_V
95 ldr r1,P1C0E_V
97 ldr r1,P1C06_V
99 ldr r1,P1C0E_V
103 ldr r1,[r0]
109 ldr r0,SCCTRL_V
114 ldr r0,DDR_07_V
115 ldr r1,[R0]
116 ldr r2,SREFRESH_MASK_V
119 ldr r2,DDR_ACTIVE_V
124 ldr r0,SREFRESH_DELAY_V