Lines Matching refs:ldr
34 ldr x0, =GICD_BASE
36 ldr x1, =GICC_BASE
39 ldr x2, =DCFG_CCSR_SVR
40 ldr w2, [x2]
43 ldr w4, =SVR_DEV(SVR_LS1043A)
49 ldr x2, =SCFG_GIC400_ALIGN
50 ldr w2, [x2]
53 ldr x0, =GICD_BASE_64K
55 ldr x1, =GICC_BASE_64K
93 ldr x0, =CCI_AUX_CONTROL_BASE(20)
94 ldr x1, =0x00000010
105 ldr w1, =SVR_DEV(SVR_LS2080A)
109 ldr x0, =CCI_AUX_CONTROL_BASE(6)
110 ldr x1, =0x00000020
112 ldr x0, =CCI_AUX_CONTROL_BASE(20)
113 ldr x1, =0x00000020
119 ldr x0, =CCI_MN_BASE
120 ldr x1, =CCI_MN_RNF_NODEID_LIST
121 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
125 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
126 ldr x1, =0x00FF000C
128 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
129 ldr x1, =0x00FF000C
131 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
132 ldr x1, =0x00FF000C
135 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
136 ldr x1, =0x00FF000C
138 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
139 ldr x1, =0x00FF000C
141 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
142 ldr x1, =0x00FF000C
145 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
146 ldr x1, =0x00FF000C
148 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
149 ldr x1, =0x00FF000C
151 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
152 ldr x1, =0x00FF000C
155 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
156 ldr x1, =0x00FF000C
158 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
159 ldr x1, =0x00FF000C
161 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
162 ldr x1, =0x00FF000C
165 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
166 ldr x1, =0x00FF000C
168 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
169 ldr x1, =0x00FF000C
171 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
172 ldr x1, =0x00FF000C
175 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
176 ldr x1, =0x00FF000C
178 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
179 ldr x1, =0x00FF000C
181 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
182 ldr x1, =0x00FF000C
188 ldr x1, =SMMU_BASE
189 ldr w0, [x1, #0x10]
202 ldr x0, =GICR_BASE
229 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
244 ldr w1, =SVR_DEV(SVR_LS2080A)
265 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
272 ldr w0, [x1] /* Region-0 Attributes Register */
280 ldr w0, [x1] /* Region-0 Access Register */
337 ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
338 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
351 ldr x0, =DCSR_DCFG_SBEESR2
353 ldr x0, =DCSR_DCFG_MBEESR2
362 ldr x1, =FSL_LSCH3_SVR
363 ldr w0, [x1]
377 ldr x2, [x0]
395 ldr x2, [x0]