Lines Matching refs:MUX_M0
25 writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */ in hi6220_uart_config()
26 writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */ in hi6220_uart_config()
33 writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */ in hi6220_uart_config()
34 writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */ in hi6220_uart_config()
35 writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */ in hi6220_uart_config()
36 writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */ in hi6220_uart_config()
45 writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */ in hi6220_uart_config()
46 writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */ in hi6220_uart_config()
47 writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */ in hi6220_uart_config()
48 writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */ in hi6220_uart_config()
112 writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */ in hi6220_mmc_config()
113 writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */ in hi6220_mmc_config()
114 writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */ in hi6220_mmc_config()
115 writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */ in hi6220_mmc_config()
116 writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */ in hi6220_mmc_config()
117 writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */ in hi6220_mmc_config()
118 writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */ in hi6220_mmc_config()
119 writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */ in hi6220_mmc_config()
120 writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */ in hi6220_mmc_config()
121 writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */ in hi6220_mmc_config()
142 writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */ in hi6220_mmc_config()
143 writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */ in hi6220_mmc_config()
144 writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */ in hi6220_mmc_config()
145 writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */ in hi6220_mmc_config()
146 writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */ in hi6220_mmc_config()
147 writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */ in hi6220_mmc_config()