Lines Matching refs:cpg
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
141 clocks = <&cpg CPG_MOD 402>;
143 resets = <&cpg 402>;
157 clocks = <&cpg CPG_MOD 912>;
159 resets = <&cpg 912>;
172 clocks = <&cpg CPG_MOD 911>;
174 resets = <&cpg 911>;
187 clocks = <&cpg CPG_MOD 910>;
189 resets = <&cpg 910>;
202 clocks = <&cpg CPG_MOD 909>;
204 resets = <&cpg 909>;
217 clocks = <&cpg CPG_MOD 908>;
219 resets = <&cpg 908>;
232 clocks = <&cpg CPG_MOD 907>;
234 resets = <&cpg 907>;
248 clocks = <&cpg CPG_MOD 303>;
251 resets = <&cpg 303>;
267 clocks = <&cpg CPG_MOD 302>;
270 resets = <&cpg 302>;
286 clocks = <&cpg CPG_MOD 301>;
289 resets = <&cpg 301>;
305 clocks = <&cpg CPG_MOD 300>;
308 resets = <&cpg 300>;
312 cpg: clock-controller@e6150000 { label
313 compatible = "renesas,r8a77980-cpg-mssr";
340 clocks = <&cpg CPG_MOD 522>;
342 resets = <&cpg 522>;
357 clocks = <&cpg CPG_MOD 407>;
359 resets = <&cpg 407>;
368 clocks = <&cpg CPG_MOD 125>;
371 resets = <&cpg 125>;
381 clocks = <&cpg CPG_MOD 124>;
384 resets = <&cpg 124>;
394 clocks = <&cpg CPG_MOD 123>;
397 resets = <&cpg 123>;
407 clocks = <&cpg CPG_MOD 122>;
410 resets = <&cpg 122>;
420 clocks = <&cpg CPG_MOD 121>;
423 resets = <&cpg 121>;
432 clocks = <&cpg CPG_MOD 931>;
434 resets = <&cpg 931>;
449 clocks = <&cpg CPG_MOD 930>;
451 resets = <&cpg 930>;
466 clocks = <&cpg CPG_MOD 929>;
468 resets = <&cpg 929>;
483 clocks = <&cpg CPG_MOD 928>;
485 resets = <&cpg 928>;
497 clocks = <&cpg CPG_MOD 927>;
499 resets = <&cpg 927>;
511 clocks = <&cpg CPG_MOD 919>;
513 resets = <&cpg 919>;
529 clocks = <&cpg CPG_MOD 520>,
530 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
537 resets = <&cpg 520>;
547 clocks = <&cpg CPG_MOD 519>,
548 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
555 resets = <&cpg 519>;
565 clocks = <&cpg CPG_MOD 518>,
566 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
573 resets = <&cpg 518>;
583 clocks = <&cpg CPG_MOD 517>,
584 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
591 resets = <&cpg 517>;
599 clocks = <&cpg CPG_MOD 319>;
601 resets = <&cpg 319>;
611 clocks = <&cpg CPG_MOD 914>,
612 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
615 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
618 resets = <&cpg 914>;
666 clocks = <&cpg CPG_MOD 812>;
668 resets = <&cpg 812>;
680 clocks = <&cpg CPG_MOD 523>;
682 resets = <&cpg 523>;
690 clocks = <&cpg CPG_MOD 523>;
692 resets = <&cpg 523>;
700 clocks = <&cpg CPG_MOD 523>;
702 resets = <&cpg 523>;
710 clocks = <&cpg CPG_MOD 523>;
712 resets = <&cpg 523>;
720 clocks = <&cpg CPG_MOD 523>;
722 resets = <&cpg 523>;
732 clocks = <&cpg CPG_MOD 207>,
733 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
740 resets = <&cpg 207>;
750 clocks = <&cpg CPG_MOD 206>,
751 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
758 resets = <&cpg 206>;
768 clocks = <&cpg CPG_MOD 204>,
769 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
776 resets = <&cpg 204>;
786 clocks = <&cpg CPG_MOD 203>,
787 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
794 resets = <&cpg 203>;
802 clocks = <&cpg CPG_MOD 304>;
804 resets = <&cpg 304>;
814 clocks = <&cpg CPG_MOD 211>;
816 resets = <&cpg 211>;
827 clocks = <&cpg CPG_MOD 210>;
829 resets = <&cpg 210>;
840 clocks = <&cpg CPG_MOD 209>;
842 resets = <&cpg 209>;
853 clocks = <&cpg CPG_MOD 208>;
855 resets = <&cpg 208>;
865 clocks = <&cpg CPG_MOD 811>;
867 resets = <&cpg 811>;
893 clocks = <&cpg CPG_MOD 810>;
897 resets = <&cpg 810>;
921 clocks = <&cpg CPG_MOD 809>;
923 resets = <&cpg 809>;
949 clocks = <&cpg CPG_MOD 808>;
951 resets = <&cpg 808>;
977 clocks = <&cpg CPG_MOD 807>;
979 resets = <&cpg 807>;
1005 clocks = <&cpg CPG_MOD 806>;
1007 resets = <&cpg 806>;
1033 clocks = <&cpg CPG_MOD 805>;
1035 resets = <&cpg 805>;
1061 clocks = <&cpg CPG_MOD 804>;
1063 resets = <&cpg 804>;
1089 clocks = <&cpg CPG_MOD 628>;
1091 resets = <&cpg 628>;
1100 clocks = <&cpg CPG_MOD 627>;
1102 resets = <&cpg 627>;
1111 clocks = <&cpg CPG_MOD 625>;
1113 resets = <&cpg 625>;
1122 clocks = <&cpg CPG_MOD 618>;
1124 resets = <&cpg 618>;
1133 clocks = <&cpg CPG_MOD 612>;
1135 resets = <&cpg 612>;
1144 clocks = <&cpg CPG_MOD 608>;
1146 resets = <&cpg 608>;
1155 clocks = <&cpg CPG_MOD 605>;
1157 resets = <&cpg 605>;
1166 clocks = <&cpg CPG_MOD 604>;
1168 resets = <&cpg 604>;
1199 clocks = <&cpg CPG_MOD 218>;
1202 resets = <&cpg 218>;
1241 clocks = <&cpg CPG_MOD 217>;
1244 resets = <&cpg 217>;
1261 clocks = <&cpg CPG_MOD 813>;
1263 resets = <&cpg 813>;
1337 clocks = <&cpg CPG_MOD 314>;
1339 resets = <&cpg 314>;
1356 clocks = <&cpg CPG_MOD 408>;
1359 resets = <&cpg 408>;
1381 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1384 resets = <&cpg 319>;
1394 clocks = <&cpg CPG_MOD 623>;
1396 resets = <&cpg 623>;
1403 clocks = <&cpg CPG_MOD 603>;
1405 resets = <&cpg 603>;
1412 clocks = <&cpg CPG_MOD 716>;
1414 resets = <&cpg 716>;
1451 clocks = <&cpg CPG_MOD 715>;
1453 resets = <&cpg 715>;
1491 clocks = <&cpg CPG_MOD 724>;
1494 resets = <&cpg 724>;
1520 clocks = <&cpg CPG_MOD 727>;
1522 resets = <&cpg 727>;