Lines Matching refs:uint32_t
27 uint32_t cpuid; /* CPUID Base Register */
28 uint32_t icsr; /* Interrupt Control and State Register */
29 uint32_t vtor; /* Vector Table Offset Register */
30 uint32_t aircr; /* App Interrupt and Reset Control Register */
31 uint32_t scr; /* offset 0x10: System Control Register */
32 uint32_t ccr; /* offset 0x14: Config and Control Register */
33 uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
34 uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
35 uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
36 uint32_t shcrs; /* offset 0x24: System Handler Control State */
37 uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
38 uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
39 uint32_t res; /* offset 0x30: reserved */
40 uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */
41 uint32_t bfar; /* offset 0x38: BusFault Address Reg */
42 uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */
59 uint32_t type; /* Type Register */
60 uint32_t ctrl; /* Control Register */
61 uint32_t rnr; /* Region Number Register */
62 uint32_t rbar; /* Region Base Address Register */
63 uint32_t rasr; /* Region Attribute and Size Register */