Lines Matching defs:at91_port
38 typedef struct at91_port { struct
39 u32 per; /* 0x00 PIO Enable Register */
40 u32 pdr; /* 0x04 PIO Disable Register */
41 u32 psr; /* 0x08 PIO Status Register */
42 u32 reserved0;
43 u32 oer; /* 0x10 Output Enable Register */
44 u32 odr; /* 0x14 Output Disable Registerr */
45 u32 osr; /* 0x18 Output Status Register */
46 u32 reserved1;
47 u32 ifer; /* 0x20 Input Filter Enable Register */
48 u32 ifdr; /* 0x24 Input Filter Disable Register */
49 u32 ifsr; /* 0x28 Input Filter Status Register */
50 u32 reserved2;
51 u32 sodr; /* 0x30 Set Output Data Register */
52 u32 codr; /* 0x34 Clear Output Data Register */
53 u32 odsr; /* 0x38 Output Data Status Register */
54 u32 pdsr; /* 0x3C Pin Data Status Register */
55 u32 ier; /* 0x40 Interrupt Enable Register */
56 u32 idr; /* 0x44 Interrupt Disable Register */
57 u32 imr; /* 0x48 Interrupt Mask Register */
58 u32 isr; /* 0x4C Interrupt Status Register */
59 u32 mder; /* 0x50 Multi-driver Enable Register */
60 u32 mddr; /* 0x54 Multi-driver Disable Register */
61 u32 mdsr; /* 0x58 Multi-driver Status Register */
62 u32 reserved3;
63 u32 pudr; /* 0x60 Pull-up Disable Register */
64 u32 puer; /* 0x64 Pull-up Enable Register */
65 u32 pusr; /* 0x68 Pad Pull-up Status Register */
66 u32 reserved4;
67 union {
88 } mux;
90 u32 ower; /* 0xA0 Output Write Enable Register */
91 u32 owdr; /* 0xA4 Output Write Disable Register */
92 u32 owsr; /* OxA8 Output Write Status Register */
116 } at91_port_t; argument