Lines Matching refs:mem
35 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) in ddr3_mem_ctrl_init() argument
51 val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
52 (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
53 (mem->impedance << CA_CS_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
54 (mem->impedance << CA_ADR_DRVR_DS_OFFSET); in ddr3_mem_ctrl_init()
59 val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | in ddr3_mem_ctrl_init()
60 (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); in ddr3_mem_ctrl_init()
65 if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, in ddr3_mem_ctrl_init()
70 writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); in ddr3_mem_ctrl_init()
71 writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14); in ddr3_mem_ctrl_init()
73 writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) in ddr3_mem_ctrl_init()
74 | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), in ddr3_mem_ctrl_init()
80 writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); in ddr3_mem_ctrl_init()
81 writel(mem->phy1_dqs, &phy1_ctrl->phy_con4); in ddr3_mem_ctrl_init()
83 writel(mem->phy0_dq, &phy0_ctrl->phy_con6); in ddr3_mem_ctrl_init()
84 writel(mem->phy1_dq, &phy1_ctrl->phy_con6); in ddr3_mem_ctrl_init()
86 writel(mem->phy0_tFS, &phy0_ctrl->phy_con10); in ddr3_mem_ctrl_init()
87 writel(mem->phy1_tFS, &phy1_ctrl->phy_con10); in ddr3_mem_ctrl_init()
89 val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | in ddr3_mem_ctrl_init()
90 (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | in ddr3_mem_ctrl_init()
91 (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | in ddr3_mem_ctrl_init()
92 (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); in ddr3_mem_ctrl_init()
97 writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), in ddr3_mem_ctrl_init()
99 writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), in ddr3_mem_ctrl_init()
104 writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), in ddr3_mem_ctrl_init()
108 writel(mem->iv_size, &dmc->ivcontrol); in ddr3_mem_ctrl_init()
110 writel(mem->memconfig, &dmc->memconfig0); in ddr3_mem_ctrl_init()
111 writel(mem->memconfig, &dmc->memconfig1); in ddr3_mem_ctrl_init()
112 writel(mem->membaseconfig0, &dmc->membaseconfig0); in ddr3_mem_ctrl_init()
113 writel(mem->membaseconfig1, &dmc->membaseconfig1); in ddr3_mem_ctrl_init()
116 writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, in ddr3_mem_ctrl_init()
120 writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | in ddr3_mem_ctrl_init()
121 mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, in ddr3_mem_ctrl_init()
127 writel(mem->timing_ref, &dmc->timingref); in ddr3_mem_ctrl_init()
128 writel(mem->timing_row, &dmc->timingrow); in ddr3_mem_ctrl_init()
129 writel(mem->timing_data, &dmc->timingdata); in ddr3_mem_ctrl_init()
130 writel(mem->timing_power, &dmc->timingpower); in ddr3_mem_ctrl_init()
133 dmc_config_prech(mem, &dmc->directcmd); in ddr3_mem_ctrl_init()
136 dmc_config_mrs(mem, &dmc->directcmd); in ddr3_mem_ctrl_init()
138 if (mem->gate_leveling_enable) { in ddr3_mem_ctrl_init()
155 val = (mem->ctrl_start_point << in ddr3_mem_ctrl_init()
157 (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | in ddr3_mem_ctrl_init()
158 (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | in ddr3_mem_ctrl_init()
159 (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | in ddr3_mem_ctrl_init()
160 (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); in ddr3_mem_ctrl_init()
201 val = (mem->ctrl_start_point << in ddr3_mem_ctrl_init()
203 (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | in ddr3_mem_ctrl_init()
204 (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | in ddr3_mem_ctrl_init()
205 (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | in ddr3_mem_ctrl_init()
206 (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | in ddr3_mem_ctrl_init()
207 (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); in ddr3_mem_ctrl_init()
215 dmc_config_prech(mem, &dmc->directcmd); in ddr3_mem_ctrl_init()
217 writel(mem->memcontrol, &dmc->memcontrol); in ddr3_mem_ctrl_init()
220 writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) in ddr3_mem_ctrl_init()
221 | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); in ddr3_mem_ctrl_init()
440 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) in ddr3_mem_ctrl_init() argument
468 mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; in ddr3_mem_ctrl_init()
469 mem->chips_per_channel = 2; in ddr3_mem_ctrl_init()
470 mem->chips_to_configure = 2; in ddr3_mem_ctrl_init()
473 mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; in ddr3_mem_ctrl_init()
502 val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | in ddr3_mem_ctrl_init()
503 (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); in ddr3_mem_ctrl_init()
529 if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, in ddr3_mem_ctrl_init()
538 val |= mem->phy0_pulld_dqs; in ddr3_mem_ctrl_init()
541 val |= mem->phy1_pulld_dqs; in ddr3_mem_ctrl_init()
548 writel(mem->concontrol | in ddr3_mem_ctrl_init()
549 (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | in ddr3_mem_ctrl_init()
550 (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), in ddr3_mem_ctrl_init()
552 writel(mem->concontrol | in ddr3_mem_ctrl_init()
553 (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | in ddr3_mem_ctrl_init()
554 (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), in ddr3_mem_ctrl_init()
592 writel(mem->memconfig, &tzasc0->memconfig0); in ddr3_mem_ctrl_init()
593 writel(mem->memconfig, &tzasc1->memconfig0); in ddr3_mem_ctrl_init()
594 writel(mem->memconfig, &tzasc0->memconfig1); in ddr3_mem_ctrl_init()
595 writel(mem->memconfig, &tzasc1->memconfig1); in ddr3_mem_ctrl_init()
598 writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, in ddr3_mem_ctrl_init()
600 writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, in ddr3_mem_ctrl_init()
607 writel(mem->timing_ref, &drex0->timingref); in ddr3_mem_ctrl_init()
608 writel(mem->timing_ref, &drex1->timingref); in ddr3_mem_ctrl_init()
609 writel(mem->timing_row, &drex0->timingrow0); in ddr3_mem_ctrl_init()
610 writel(mem->timing_row, &drex1->timingrow0); in ddr3_mem_ctrl_init()
611 writel(mem->timing_data, &drex0->timingdata0); in ddr3_mem_ctrl_init()
612 writel(mem->timing_data, &drex1->timingdata0); in ddr3_mem_ctrl_init()
613 writel(mem->timing_power, &drex0->timingpower0); in ddr3_mem_ctrl_init()
614 writel(mem->timing_power, &drex1->timingpower0); in ddr3_mem_ctrl_init()
623 dmc_config_mrs(mem, &drex0->directcmd); in ddr3_mem_ctrl_init()
624 dmc_config_mrs(mem, &drex1->directcmd); in ddr3_mem_ctrl_init()
679 for (chip = 0; chip < mem->chips_to_configure; chip++) { in ddr3_mem_ctrl_init()
690 if (mem->gate_leveling_enable) { in ddr3_mem_ctrl_init()
723 for (chip = 0; chip < mem->chips_to_configure; chip++) { in ddr3_mem_ctrl_init()
778 for (chip = 0; chip < mem->chips_to_configure; chip++) { in ddr3_mem_ctrl_init()
816 dmc_config_prech(mem, &drex0->directcmd); in ddr3_mem_ctrl_init()
817 dmc_config_prech(mem, &drex1->directcmd); in ddr3_mem_ctrl_init()
819 writel(mem->memcontrol, &drex0->memcontrol); in ddr3_mem_ctrl_init()
820 writel(mem->memcontrol, &drex1->memcontrol); in ddr3_mem_ctrl_init()
827 writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | in ddr3_mem_ctrl_init()
828 (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| in ddr3_mem_ctrl_init()
831 writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | in ddr3_mem_ctrl_init()
832 (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| in ddr3_mem_ctrl_init()