Lines Matching refs:CLK_ROOT_ON
149 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
152 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
155 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_enable_bypass()
161 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_disable_bypass()
163 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_disable_bypass()
281 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
287 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
293 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
299 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
314 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
330 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | in init_clk_usdhc()
336 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | in init_clk_usdhc()
342 clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON | in init_clk_usdhc()
357 clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); in init_clk_ecspi()
362 clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); in init_clk_ecspi()
367 clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); in init_clk_ecspi()
383 clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | in init_nand_clk()
416 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | in clock_init()
432 clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); in clock_init()
434 clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); in clock_init()
438 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | in clock_init()
443 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | in clock_init()
447 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | in clock_init()
449 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in clock_init()
818 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | in set_clk_eqos()
823 target = CLK_ROOT_ON | enet1_ref | in set_clk_eqos()
828 target = CLK_ROOT_ON | in set_clk_eqos()
908 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | in set_clk_enet()
913 target = CLK_ROOT_ON | enet1_ref | in set_clk_enet()
918 target = CLK_ROOT_ON | in set_clk_enet()