Lines Matching refs:ana_pll
18 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; variable
31 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll()
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
41 pllout_div = readl(&ana_pll->frac_pllout_div_cfg); in decode_frac_pll()
102 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); in decode_sscg_pll()
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
104 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); in decode_sscg_pll()
117 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
119 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2); in decode_sscg_pll()
124 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
126 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2); in decode_sscg_pll()
131 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
133 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2); in decode_sscg_pll()
209 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg); in decode_sscg_pll()
582 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; in dram_pll_init()
583 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2; in dram_pll_init()
664 pll_cfg0 = &ana_pll->arm_pll_cfg0; in frac_pll_init()
665 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
727 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK | in clock_init()
733 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK | in clock_init()