Lines Matching refs:pll_cfg0
24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
31 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll()
45 if (pll_cfg0 & FRAC_PLL_PD_MASK) in decode_frac_pll()
49 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0) in decode_frac_pll()
52 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK; in decode_frac_pll()
63 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK) in decode_frac_pll()
66 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >> in decode_frac_pll()
68 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
102 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); in decode_sscg_pll()
117 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); in decode_sscg_pll()
124 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0); in decode_sscg_pll()
131 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0); in decode_sscg_pll()
202 if (pll_cfg0 & SSCG_PLL_PD_MASK) in decode_sscg_pll()
206 if ((pll_cfg0 & pll_clke) == 0) in decode_sscg_pll()
212 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK; in decode_sscg_pll()
224 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) || in decode_sscg_pll()
225 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK)) in decode_sscg_pll()
658 void __iomem *pll_cfg0, __iomem *pll_cfg1; in frac_pll_init() local
664 pll_cfg0 = &ana_pll->arm_pll_cfg0; in frac_pll_init()
684 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); in frac_pll_init()
687 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
688 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
690 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); in frac_pll_init()
691 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
695 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK); in frac_pll_init()