Lines Matching refs:clk_sel
324 static u32 get_standard_pll_sel_clk(u32 clk_sel) in get_standard_pll_sel_clk() argument
328 switch (clk_sel & 0x3) { in get_standard_pll_sel_clk()
351 unsigned int clk_sel, freq, reg, pred, podf; in get_uart_clk() local
354 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); in get_uart_clk()
355 freq = get_standard_pll_sel_clk(clk_sel); in get_uart_clk()
370 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; in imx_get_cspiclk() local
376 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1); in imx_get_cspiclk()
377 freq = get_standard_pll_sel_clk(clk_sel); in imx_get_cspiclk()
387 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; in get_esdhc_clk() local
393 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1); in get_esdhc_clk()
398 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1); in get_esdhc_clk()
416 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1)); in get_esdhc_clk()
799 s32 shift = 0, clk_sel, div = 1; in config_ddr_clk() local
810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in config_ddr_clk()
811 switch (clk_sel) { in config_ddr_clk()