Lines Matching refs:mdscr
43 writel(0x04008050, &mmdc0->mdscr); in precharge_all()
44 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
48 writel(0x04008058, &mmdc0->mdscr); in precharge_all()
49 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
159 writel(0x00808231, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
214 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
246 writel(0, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
333 writel(0x00008020, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
335 writel(0x00008028, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
338 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in mmdc_do_dqs_calibration()
576 writel(0x0, &mmdc0->mdscr); /* CS0 */ in mmdc_do_dqs_calibration()
579 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0); in mmdc_do_dqs_calibration()
1185 mmdc0->mdscr = (u32)(1 << 15); /* config request */ in mx6_lpddr2_cfg()
1229 mmdc0->mdscr = MR(63, 0, 3, cs); in mx6_lpddr2_cfg()
1234 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1237 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1240 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1243 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1263 mmdc0->mdscr = 0x00000000; in mx6_lpddr2_cfg()
1479 mmdc0->mdscr = (u32)(1 << 15); /* config request */ in mx6_ddr3_cfg()
1528 mmdc0->mdscr = MR(val, 2, 3, cs); in mx6_ddr3_cfg()
1531 mmdc0->mdscr = MR(0, 3, 3, cs); in mx6_ddr3_cfg()
1536 mmdc0->mdscr = MR(val, 1, 3, cs); in mx6_ddr3_cfg()
1543 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_ddr3_cfg()
1546 mmdc0->mdscr = MR(val, 0, 4, cs); in mx6_ddr3_cfg()
1643 mmdc0->mdscr = 0x00000000; in mx6_ddr3_cfg()