Lines Matching refs:cpu
106 #define imx_cpu_gpr_entry_offset(cpu) \ argument
107 (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
108 #define imx_cpu_gpr_para_offset(cpu) \ argument
109 (imx_cpu_gpr_entry_offset(cpu) + 4)
139 static inline void psci_set_state(int cpu, u8 state) in psci_set_state() argument
141 psci_state[cpu] = state; in psci_set_state()
151 __secure void imx_gpcv2_set_core_power(int cpu, bool pdn) in imx_gpcv2_set_core_power() argument
154 u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0; in imx_gpcv2_set_core_power()
155 u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 : in imx_gpcv2_set_core_power()
171 __secure void imx_enable_cpu_ca7(int cpu, bool enable) in imx_enable_cpu_ca7() argument
175 mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); in imx_enable_cpu_ca7()
183 u32 cpu = psci_get_cpu_id(); in psci_arch_cpu_entry() local
185 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); in psci_arch_cpu_entry()
191 u32 cpu = mpidr & MPIDR_AFF0; in psci_cpu_on() local
196 if (cpu >= IMX7D_PSCI_NR_CPUS) in psci_cpu_on()
199 if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) in psci_cpu_on()
202 if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING) in psci_cpu_on()
205 psci_save(cpu, ep, context_id); in psci_cpu_on()
207 writel((u32)psci_cpu_entry, imx_cpu_gpr_entry_offset(cpu)); in psci_cpu_on()
209 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); in psci_cpu_on()
211 imx_gpcv2_set_core_power(cpu, true); in psci_cpu_on()
212 imx_enable_cpu_ca7(cpu, true); in psci_cpu_on()
219 int cpu; in psci_cpu_off() local
221 cpu = psci_get_cpu_id(); in psci_cpu_off()
224 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); in psci_cpu_off()
226 imx_enable_cpu_ca7(cpu, false); in psci_cpu_off()
227 imx_gpcv2_set_core_power(cpu, false); in psci_cpu_off()
232 writel(IMX_CPU_SYNC_OFF, imx_cpu_gpr_para_offset(cpu)); in psci_cpu_off()
282 u32 cpu = target_affinity & MPIDR_AFF0; in psci_affinity_info() local
290 if (cpu >= IMX7D_PSCI_NR_CPUS) in psci_affinity_info()
294 if (readl(imx_cpu_gpr_para_offset(cpu)) == IMX_CPU_SYNC_OFF) { in psci_affinity_info()
295 imx_enable_cpu_ca7(cpu, false); in psci_affinity_info()
296 imx_gpcv2_set_core_power(cpu, false); in psci_affinity_info()
297 writel(IMX_CPU_SYNC_ON, imx_cpu_gpr_para_offset(cpu)); in psci_affinity_info()
300 return psci_state[cpu]; in psci_affinity_info()
393 static __secure void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn) in imx_gpcv2_set_cpu_power_gate_by_lpm() argument
398 if (cpu == 0) { in imx_gpcv2_set_cpu_power_gate_by_lpm()
406 if (cpu == 1) { in imx_gpcv2_set_cpu_power_gate_by_lpm()