Lines Matching refs:ddr_phy
369 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_pctrl_reset() local
387 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
391 clrsetbits_le32(&ddr_phy->ddrphy_reg1, in phy_pctrl_reset()
400 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_dll_bypass_set() local
404 LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a); in phy_dll_bypass_set()
409 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6); in phy_dll_bypass_set()
415 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
418 LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a); in phy_dll_bypass_set()
424 &ddr_phy->ddrphy_reg6); in phy_dll_bypass_set()
430 &ddr_phy->ddrphy_reg9); in phy_dll_bypass_set()
435 CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19); in phy_dll_bypass_set()
439 LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8); in phy_dll_bypass_set()
441 RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11); in phy_dll_bypass_set()
485 struct rk3036_ddr_phy *ddr_phy = priv->phy; in data_training() local
493 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, in data_training()
497 while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != in data_training()
502 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, in data_training()
627 struct rk3036_ddr_phy *ddr_phy = priv->phy; in phy_cfg() local
634 &ddr_phy->ddrphy_reg2); in phy_cfg()
636 clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
638 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16); in phy_cfg()
639 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22); in phy_cfg()
640 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25); in phy_cfg()
641 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26); in phy_cfg()
642 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27); in phy_cfg()
643 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28); in phy_cfg()