Lines Matching refs:sys_reg2
87 u32 sys_reg2 = readl(reg); in rockchip_sdram_size() local
89 u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT) in rockchip_sdram_size()
92 dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; in rockchip_sdram_size()
93 debug("%s %x %x\n", __func__, (u32)reg, sys_reg2); in rockchip_sdram_size()
95 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & in rockchip_sdram_size()
97 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & in rockchip_sdram_size()
100 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); in rockchip_sdram_size()
106 SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >> in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
118 SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >> in rockchip_sdram_size()
123 cs1_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
132 cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
135 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & in rockchip_sdram_size()
137 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & in rockchip_sdram_size()
140 dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & in rockchip_sdram_size()