Lines Matching refs:dx
350 writel(0x0, &mctl_phy->dx[2].gcr[0]); in mctl_com_init()
351 writel(0x0, &mctl_phy->dx[3].gcr[0]); in mctl_com_init()
363 val = readl(&mctl_phy->dx[i].bdlr0); in mctl_bit_delay_set()
366 writel(val, &mctl_phy->dx[i].bdlr0); in mctl_bit_delay_set()
368 val = readl(&mctl_phy->dx[i].bdlr1); in mctl_bit_delay_set()
371 writel(val, &mctl_phy->dx[i].bdlr1); in mctl_bit_delay_set()
373 val = readl(&mctl_phy->dx[i].bdlr2); in mctl_bit_delay_set()
376 writel(val, &mctl_phy->dx[i].bdlr2); in mctl_bit_delay_set()
381 val = readl(&mctl_phy->dx[i].bdlr3); in mctl_bit_delay_set()
384 writel(val, &mctl_phy->dx[i].bdlr3); in mctl_bit_delay_set()
386 val = readl(&mctl_phy->dx[i].bdlr4); in mctl_bit_delay_set()
389 writel(val, &mctl_phy->dx[i].bdlr4); in mctl_bit_delay_set()
391 val = readl(&mctl_phy->dx[i].bdlr5); in mctl_bit_delay_set()
394 writel(val, &mctl_phy->dx[i].bdlr5); in mctl_bit_delay_set()
396 val = readl(&mctl_phy->dx[i].bdlr6); in mctl_bit_delay_set()
399 writel(val, &mctl_phy->dx[i].bdlr6); in mctl_bit_delay_set()
441 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); in mctl_channel_init()
443 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555); in mctl_channel_init()
445 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010); in mctl_channel_init()
506 writel(0x00000909, &mctl_phy->dx[i].gcr[5]); in mctl_channel_init()
513 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val); in mctl_channel_init()
519 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val); in mctl_channel_init()
528 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); in mctl_channel_init()
536 debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0])); in mctl_channel_init()