Lines Matching refs:CLOCK_ID_PERIPH
568 if (clkid != CLOCK_ID_PERIPH) in clock_get_rate()
612 if (clkid == CLOCK_ID_PERIPH) { in clock_set_rate()
678 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); in clock_verify()
695 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); in clock_init()
707 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); in clock_init()
769 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); in tegra30_set_up_pllp()
774 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); in tegra30_set_up_pllp()
779 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); in tegra30_set_up_pllp()
797 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
803 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
808 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
814 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()