Lines Matching refs:padctl
99 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) in tegra_xusb_padctl_enable() argument
103 if (padctl->enable++ > 0) in tegra_xusb_padctl_enable()
106 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
108 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
112 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
114 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
118 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
120 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
125 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) in tegra_xusb_padctl_disable() argument
129 if (padctl->enable == 0) { in tegra_xusb_padctl_disable()
134 if (--padctl->enable > 0) in tegra_xusb_padctl_disable()
137 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
139 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
143 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
145 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
149 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
151 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
160 err = tegra_xusb_padctl_enable(phy->padctl); in phy_prepare()
173 return tegra_xusb_padctl_disable(phy->padctl); in phy_unprepare()
231 struct tegra_xusb_padctl *padctl = phy->padctl; in pcie_phy_enable() local
237 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
240 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
242 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
245 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
247 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
249 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
251 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
253 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
255 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
257 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
259 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
264 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
266 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
270 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
272 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
274 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
276 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
278 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
282 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
295 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
305 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
307 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
314 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
324 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
326 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
332 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
342 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
345 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
351 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
361 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
363 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
369 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
379 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
381 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
403 .padctl = &padctl,
453 value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra_xusb_padctl_exit()
463 padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra_xusb_padctl_exit()
465 value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra_xusb_padctl_exit()
470 padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra_xusb_padctl_exit()
473 while (padctl.enable) in tegra_xusb_padctl_exit()
474 tegra_xusb_padctl_disable(&padctl); in tegra_xusb_padctl_exit()