Lines Matching refs:tmp
31 u32 tmp; in set_r5_halt_mode() local
33 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_halt_mode()
35 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
37 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
38 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_halt_mode()
41 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_halt_mode()
43 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
45 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; in set_r5_halt_mode()
46 writel(tmp, &rpu_base->rpu1_cfg); in set_r5_halt_mode()
52 u32 tmp; in set_r5_tcm_mode() local
54 tmp = readl(&rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
56 tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; in set_r5_tcm_mode()
57 tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | in set_r5_tcm_mode()
60 tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; in set_r5_tcm_mode()
61 tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | in set_r5_tcm_mode()
65 writel(tmp, &rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
70 u32 tmp; in release_r5_reset() local
72 tmp = readl(&crlapb_base->rst_cpu_r5); in release_r5_reset()
73 tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK | in release_r5_reset()
78 tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK; in release_r5_reset()
80 writel(tmp, &crlapb_base->rst_cpu_r5); in release_r5_reset()
85 u32 tmp; in enable_clock_r5() local
87 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()
88 tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; in enable_clock_r5()
89 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()