Lines Matching refs:ddr_regs
192 void __iomem *ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, in qca956x_ddr_init() local
207 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); in qca956x_ddr_init()
210 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); in qca956x_ddr_init()
213 writel(ctl_config, ddr_regs + QCA956X_DDR_REG_CTL_CONF); in qca956x_ddr_init()
216 writel(cycle_val, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); in qca956x_ddr_init()
219 writel(0x74444444, ddr_regs + QCA956X_DDR_REG_BURST); in qca956x_ddr_init()
222 writel(0x44444444, ddr_regs + QCA956X_DDR_REG_BURST2); in qca956x_ddr_init()
225 writel(DDR_FSM_WAIT_CTRL_VAL, ddr_regs + QCA956X_DDR_REG_FSM_WAIT_CTRL); in qca956x_ddr_init()
228 writel(0xfffff, ddr_regs + QCA956X_DDR_REG_TIMEOUT_MAX); in qca956x_ddr_init()
231 writel(ddr_config, ddr_regs + AR71XX_DDR_REG_CONFIG); in qca956x_ddr_init()
234 writel(ddr_config2, ddr_regs + AR71XX_DDR_REG_CONFIG2); in qca956x_ddr_init()
237 writel(ddr_config3, ddr_regs + QCA956X_DDR_REG_DDR3_CONFIG); in qca956x_ddr_init()
240 writel(CFG_DDR2_EN_TWL_VAL, ddr_regs + QCA956X_DDR_REG_DDR2_CONFIG); in qca956x_ddr_init()
243 writel(ddr_config2 | 0x80, ddr_regs + AR71XX_DDR_REG_CONFIG2); /* CKE Enable */ in qca956x_ddr_init()
246 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */ in qca956x_ddr_init()
249 writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR2); in qca956x_ddr_init()
250 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR2 */ in qca956x_ddr_init()
253 writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR3); in qca956x_ddr_init()
254 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR3 */ in qca956x_ddr_init()
258 writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR); in qca956x_ddr_init()
261 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ in qca956x_ddr_init()
264 writel(mod_val_init, ddr_regs + AR71XX_DDR_REG_MODE); in qca956x_ddr_init()
267 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR Write */ in qca956x_ddr_init()
270 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */ in qca956x_ddr_init()
273 writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */ in qca956x_ddr_init()
276 writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */ in qca956x_ddr_init()
280 writel(mod_val, ddr_regs + AR71XX_DDR_REG_MODE); in qca956x_ddr_init()
283 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR write */ in qca956x_ddr_init()
286 writel(CFG_DDR2_EXT_MODE_VAL1, ddr_regs + AR71XX_DDR_REG_EMR); in qca956x_ddr_init()
289 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ in qca956x_ddr_init()
292 writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR); in qca956x_ddr_init()
295 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ in qca956x_ddr_init()
298 writel(CFG_DDR2_REFRESH_VAL, ddr_regs + AR71XX_DDR_REG_REFRESH); in qca956x_ddr_init()
301 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); in qca956x_ddr_init()
302 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); in qca956x_ddr_init()
303 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL2); in qca956x_ddr_init()
304 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL3); in qca956x_ddr_init()