Lines Matching refs:mc_reset
70 u32 dq_dly, u32 dqs_dly, mc_reset_t mc_reset, u32 bw) in mc_ddr_init() argument
74 mc_reset(1); in mc_ddr_init()
76 mc_reset(0); in mc_ddr_init()
109 param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT); in ddr1_init()
120 param->dqs_dly, param->mc_reset, bw); in ddr1_init()
140 param->dqs_dly, param->mc_reset, bw); in ddr1_init()
154 param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT); in ddr2_init()
165 param->dqs_dly, param->mc_reset, bw); in ddr2_init()
197 param->dqs_dly, param->mc_reset, bw); in ddr2_init()
204 static void mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0, in mc_sdr_init() argument
207 mc_reset(1); in mc_sdr_init()
209 mc_reset(0); in mc_sdr_init()
232 mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0, in sdr_init()
249 mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0, in sdr_init()