Lines Matching refs:param

102 void ddr1_init(struct mc_ddr_init_param *param)  in ddr1_init()  argument
108 	mc_ddr_init(param->memc, &param->cfgs[DRAM_8MB], param->dq_dly,  in ddr1_init()
109 		    param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT);  in ddr1_init()
119 	mc_ddr_init(param->memc, &param->cfgs[DRAM_128MB], param->dq_dly,  in ddr1_init()
120 		    param->dqs_dly, param->mc_reset, bw);  in ddr1_init()
139 	mc_ddr_init(param->memc, &param->cfgs[sz], param->dq_dly,  in ddr1_init()
140 		    param->dqs_dly, param->mc_reset, bw);  in ddr1_init()
143 	param->memsize = dram_size[sz];  in ddr1_init()
144 	param->bus_width = bw;  in ddr1_init()
147 void ddr2_init(struct mc_ddr_init_param *param)  in ddr2_init()  argument
153 	mc_ddr_init(param->memc, &param->cfgs[DRAM_32MB], param->dq_dly,  in ddr2_init()
154 		    param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT);  in ddr2_init()
164 	mc_ddr_init(param->memc, &param->cfgs[DRAM_256MB], param->dq_dly,  in ddr2_init()
165 		    param->dqs_dly, param->mc_reset, bw);  in ddr2_init()
196 	mc_ddr_init(param->memc, &param->cfgs[sz], param->dq_dly,  in ddr2_init()
197 		    param->dqs_dly, param->mc_reset, bw);  in ddr2_init()
200 	param->memsize = dram_size[sz];  in ddr2_init()
201 	param->bus_width = bw;  in ddr2_init()
223 void sdr_init(struct mc_ddr_init_param *param)  in sdr_init()  argument
228 	cfg1 = param->sdr_cfg1 | SDRAM_INIT_START;  in sdr_init()
232 	mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0,  in sdr_init()
249 	mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0,  in sdr_init()
253 	param->memsize = dram_size[sz];  in sdr_init()