Lines Matching refs:blob
33 extern void ft_qe_setup(void *blob);
34 extern void ft_fixup_num_cores(void *blob);
35 extern void ft_srio_setup(void *blob);
40 void ft_fixup_cpu(void *blob, u64 memory_limit) in ft_fixup_cpu() argument
53 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); in ft_fixup_cpu()
55 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); in ft_fixup_cpu()
62 fdt_setprop_string(blob, off, "status", in ft_fixup_cpu()
65 fdt_setprop_string(blob, off, "status", in ft_fixup_cpu()
81 fdt_setprop(blob, off, "cpu-release-addr", in ft_fixup_cpu()
85 fdt_setprop_string(blob, off, "enable-method", in ft_fixup_cpu()
90 off = fdt_node_offset_by_prop_value(blob, off, in ft_fixup_cpu()
106 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, in ft_fixup_cpu()
116 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); in ft_fixup_cpu()
129 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096); in ft_fixup_cpu()
139 off = fdt_add_mem_rsv(blob, in ft_fixup_cpu()
147 off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, in ft_fixup_cpu()
153 off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, in ft_fixup_cpu()
164 static inline void ft_fixup_l3cache(void *blob, int off) in ft_fixup_l3cache() argument
175 fdt_setprop(blob, off, "cache-unified", NULL, 0); in ft_fixup_l3cache()
176 fdt_setprop_cell(blob, off, "cache-block-size", line_size); in ft_fixup_l3cache()
177 fdt_setprop_cell(blob, off, "cache-size", size); in ft_fixup_l3cache()
178 fdt_setprop_cell(blob, off, "cache-sets", num_sets); in ft_fixup_l3cache()
179 fdt_setprop_cell(blob, off, "cache-level", 3); in ft_fixup_l3cache()
181 fdt_setprop_cell(blob, off, "cache-stash-id", 1); in ft_fixup_l3cache()
191 static inline void ft_fixup_l2cache_compatible(void *blob, int off) in ft_fixup_l2cache_compatible() argument
216 fdt_setprop(blob, off, "compatible", buf, len); in ft_fixup_l2cache_compatible()
254 static inline void ft_fixup_l2cache(void *blob) in ft_fixup_l2cache() argument
264 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); in ft_fixup_l2cache()
270 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); in ft_fixup_l2cache()
277 off = fdt_node_offset_by_phandle(blob, *ph); in ft_fixup_l2cache()
283 ft_fixup_l2cache_compatible(blob, off); in ft_fixup_l2cache()
284 fdt_setprop(blob, off, "cache-unified", NULL, 0); in ft_fixup_l2cache()
285 fdt_setprop_cell(blob, off, "cache-block-size", line_size); in ft_fixup_l2cache()
286 fdt_setprop_cell(blob, off, "cache-size", size); in ft_fixup_l2cache()
287 fdt_setprop_cell(blob, off, "cache-sets", num_sets); in ft_fixup_l2cache()
288 fdt_setprop_cell(blob, off, "cache-level", 2); in ft_fixup_l2cache()
294 static inline void ft_fixup_l2cache(void *blob) in ft_fixup_l2cache() argument
317 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); in ft_fixup_l2cache()
320 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); in ft_fixup_l2cache()
327 l2_off = fdt_node_offset_by_phandle(blob, *ph); in ft_fixup_l2cache()
335 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); in ft_fixup_l2cache()
339 fdt_setprop_cell(blob, l2_off, "cache-stash-id", in ft_fixup_l2cache()
344 fdt_setprop_cell(blob, l2_off, "cache-stash-id", in ft_fixup_l2cache()
350 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); in ft_fixup_l2cache()
351 fdt_setprop_cell(blob, l2_off, "cache-block-size", in ft_fixup_l2cache()
353 fdt_setprop_cell(blob, l2_off, "cache-size", size); in ft_fixup_l2cache()
354 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); in ft_fixup_l2cache()
355 fdt_setprop_cell(blob, l2_off, "cache-level", 2); in ft_fixup_l2cache()
356 ft_fixup_l2cache_compatible(blob, l2_off); in ft_fixup_l2cache()
360 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); in ft_fixup_l2cache()
369 off = fdt_node_offset_by_prop_value(blob, off, in ft_fixup_l2cache()
373 l3_off = fdt_node_offset_by_phandle(blob, l3_off); in ft_fixup_l2cache()
378 ft_fixup_l3cache(blob, l3_off); in ft_fixup_l2cache()
385 static inline void ft_fixup_cache(void *blob) in ft_fixup_cache() argument
389 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); in ft_fixup_cache()
403 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); in ft_fixup_cache()
404 fdt_setprop_cell(blob, off, "d-cache-size", dsize); in ft_fixup_cache()
405 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); in ft_fixup_cache()
409 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); in ft_fixup_cache()
411 fdt_setprop_cell(blob, off, "cache-stash-id", in ft_fixup_cache()
422 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); in ft_fixup_cache()
423 fdt_setprop_cell(blob, off, "i-cache-size", isize); in ft_fixup_cache()
424 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); in ft_fixup_cache()
426 off = fdt_node_offset_by_prop_value(blob, off, in ft_fixup_cache()
430 ft_fixup_l2cache(blob); in ft_fixup_cache()
448 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, in ft_fixup_clks() argument
452 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); in ft_fixup_clks()
455 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); in ft_fixup_clks()
463 static void ft_fixup_dpaa_clks(void *blob) in ft_fixup_dpaa_clks() argument
469 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, in ft_fixup_dpaa_clks()
473 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, in ft_fixup_dpaa_clks()
479 do_fixup_by_compat_u32(blob, "fsl,qman", in ft_fixup_dpaa_clks()
484 do_fixup_by_compat_u32(blob, "fsl,pme", in ft_fixup_dpaa_clks()
493 static void ft_fixup_qe_snum(void *blob) in ft_fixup_qe_snum() argument
500 do_fixup_by_compat_u32(blob, "fsl,qe", in ft_fixup_qe_snum()
503 do_fixup_by_compat_u32(blob, "fsl,qe", in ft_fixup_qe_snum()
532 void fdt_fixup_dma3(void *blob) argument
559 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
562 fdt_status_disabled(blob, nodeoff);
575 static void fdt_fixup_l2_switch(void *blob) argument
582 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
594 fdt_setprop(blob, node, "local-mac-address", l2swaddr,
601 void ft_cpu_setup(void *blob, struct bd_info *bd) argument
610 fdt_fixup_crypto_node(blob, 0);
616 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
620 fdt_add_enet_stashing(blob);
625 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
628 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
631 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
633 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
635 fdt_setprop(blob, off, "clock-frequency", &val, 4);
636 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
639 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
643 ft_qe_setup(blob);
644 ft_fixup_qe_snum(blob);
648 fdt_fixup_fman_firmware(blob);
652 do_fixup_by_compat_u32(blob, "ns16550",
657 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
660 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
665 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
667 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
669 do_fixup_by_compat_u32(blob, "fsl,mpic",
672 do_fixup_by_compat_u32(blob, "fsl,mpic",
676 fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
679 ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
680 ft_fixup_num_cores(blob);
683 ft_fixup_cache(blob);
686 fdt_fixup_esdhc(blob, bd);
689 ft_fixup_dpaa_clks(blob);
692 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
695 fdt_fixup_bportals(blob);
699 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
703 fdt_fixup_qportals(blob);
707 ft_srio_setup(blob);
716 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
724 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
727 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
730 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
733 fdt_fixup_usb(blob);
735 fdt_fixup_l2_switch(blob);
737 fdt_fixup_dma3(blob);
849 void fdt_del_diu(void *blob) argument
853 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
855 fdt_del_node(blob, nodeoff);