Lines Matching refs:pic
28 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; in interrupt_init_cpu() local
39 out_be32(&pic->gcr, MPC85xx_PICGCR_RST); in interrupt_init_cpu()
40 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) in interrupt_init_cpu()
42 out_be32(&pic->gcr, MPC85xx_PICGCR_M); in interrupt_init_cpu()
43 in_be32(&pic->gcr); in interrupt_init_cpu()
51 pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ in interrupt_init_cpu()
52 debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1); in interrupt_init_cpu()
54 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ in interrupt_init_cpu()
55 debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2); in interrupt_init_cpu()
57 pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ in interrupt_init_cpu()
58 debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3); in interrupt_init_cpu()
61 pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ in interrupt_init_cpu()
62 debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8); in interrupt_init_cpu()
65 pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ in interrupt_init_cpu()
66 debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9); in interrupt_init_cpu()
69 pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ in interrupt_init_cpu()
70 debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10); in interrupt_init_cpu()
73 pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ in interrupt_init_cpu()
74 debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11); in interrupt_init_cpu()
77 pic->ctpr=0; /* 40080 clear current task priority register */ in interrupt_init_cpu()