Lines Matching refs:li
79 li r1,MSR_DE
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
103 li r27,0
106 1: li r27,1 /* Remember for later that we have the erratum */
111 li r4,0x48
169 li r0,2
225 li \scratch, 0
237 li \scratch, 0
254 li r4,CriticalInput@l
256 li r4,MachineCheck@l
258 li r4,DataStorage@l
260 li r4,InstStorage@l
262 li r4,ExtInterrupt@l
264 li r4,Alignment@l
266 li r4,ProgramCheck@l
268 li r4,FPUnavailable@l
270 li r4,SystemCall@l
273 li r4,Decrementer@l
275 li r4,IntervalTimer@l
277 li r4,WatchdogTimer@l
279 li r4,DataTLBError@l
281 li r4,InstructionTLBError@l
283 li r4,DebugBreakpoint@l
288 li r0,0x0000
314 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
359 li r2, 0
370 li r2, 0xF80
411 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
418 li r3, 0
614 li r1, 0
683 li r4, 33 /* stash id */
733 li r2,(32 + 0)
812 li r0, 0
832 li r6, 0 /* DCSR effective address */
834 li r3, MAS3_SW|MAS3_SR
835 li r4, 0
848 li r3, 1
923 li r3, 0
931 li r3, 0
938 li r3, 0
1111 li r0,0
1165 li r0,0
1180 li r0,0
1276 li r22,0
1286 li r4,0
1508 li r3,0
1542 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1637 li r0,__got2_entries@sectoff@l
1654 li r0,__fixup_entries@sectoff@l
1679 li r0,0
1783 li r4,32