Lines Matching refs:r4
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
93 cmpw r3,r4
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
98 cmpw r3,r4
111 li r4,0x48
112 rlwimi r3,r4,0,0x1f8
137 and. r4, r3, r2
157 andc r4, r3, r2
160 mtspr SPRN_L2CSR0,r4
254 li r4,CriticalInput@l
255 mtspr IVOR0,r4 /* 0: Critical input */
256 li r4,MachineCheck@l
257 mtspr IVOR1,r4 /* 1: Machine check */
258 li r4,DataStorage@l
259 mtspr IVOR2,r4 /* 2: Data storage */
260 li r4,InstStorage@l
261 mtspr IVOR3,r4 /* 3: Instruction storage */
262 li r4,ExtInterrupt@l
263 mtspr IVOR4,r4 /* 4: External interrupt */
264 li r4,Alignment@l
265 mtspr IVOR5,r4 /* 5: Alignment */
266 li r4,ProgramCheck@l
267 mtspr IVOR6,r4 /* 6: Program check */
268 li r4,FPUnavailable@l
269 mtspr IVOR7,r4 /* 7: floating point unavailable */
270 li r4,SystemCall@l
271 mtspr IVOR8,r4 /* 8: System call */
273 li r4,Decrementer@l
274 mtspr IVOR10,r4 /* 10: Decrementer */
275 li r4,IntervalTimer@l
276 mtspr IVOR11,r4 /* 11: Interval timer */
277 li r4,WatchdogTimer@l
278 mtspr IVOR12,r4 /* 12: Watchdog timer */
279 li r4,DataTLBError@l
280 mtspr IVOR13,r4 /* 13: Data TLB error */
281 li r4,InstructionTLBError@l
282 mtspr IVOR14,r4 /* 14: Instruction TLB error */
283 li r4,DebugBreakpoint@l
284 mtspr IVOR15,r4 /* 15: Debug */
415 mfspr r4, SPRN_TLB1CFG
416 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
433 2: cmpw r3, r4
683 li r4, 33 /* stash id */
684 stw r4, 4(r3)
685 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
686 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
688 stw r4, 0(r3) /* invalidate L2 */
694 and. r1, r0, r4
698 lis r4, (L2CSR0_L2PE)@h
699 ori r4, r4, (L2CSR0_L2PE)@l
701 stw r4, 0(r3) /* enable L2 parity/ECC error checking */
707 and. r1, r0, r4
710 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
711 ori r4, r4, (L2CSR0_L2REP_MODE)@l
713 stw r4, 0(r3) /* enable L2 */
719 and. r1, r0, r4
799 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
800 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
805 mtspr MAS7, r4
835 li r4, 0
840 mtspr MAS7, r4
849 addis r4, r7, CTBENR@ha
850 stw r3, CTBENR@l(r4)
851 lwz r3, CTBENR@l(r4)
857 lis r4, \value@h
859 ori r4, r4, \value@l
865 lis r4, \value@h
867 ori r4, r4, \value@l
888 mfspr r4, MAS2
889 rlwimi r4, r15, 0, MAS2_I
890 rlwimi r4, r15, 0, MAS2_G
891 mtspr MAS2, r4
905 mfspr r4,SPRN_L1CSR1
906 and. r4,r4,r3
916 mfspr r4,SPRN_L1CSR1
917 and. r4,r4,r3
990 stw r4, 0(r3)
1162 lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
1163 ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
1167 1: subi r4,r4,4
1168 stw r0,0(r4)
1169 cmplw r4,r3
1173 lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
1174 ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
1177 stw r3,GD_MALLOC_BASE(r4)
1229 mfspr r4,DAR
1230 stw r4,_DAR(r21)
1286 li r4,0
1287 ori r4,r4,MSR_EE
1288 andc r28,r28,r4
1344 mfspr r4,L1CSR1
1345 ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
1346 oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
1347 mtspr L1CSR1,r4
1385 lis r4,0
1386 ori r4,r4,L1CSR0_DCE
1387 andc r3,r3,r4
1413 stb r4,0x0000(r3)
1423 sth r4,0x0000(r3)
1433 sthbrx r4,r0,r3
1443 stw r4,0x0000(r3)
1453 stwbrx r4,r0,r3
1502 mtspr MAS1,r4
1532 mr r9,r4 /* Save copy of Init Data pointer */
1538 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1539 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1541 sub r5,r5,r4
1551 sub r15,r10,r4
1562 cmplw cr1,r3,r4
1570 la r8,-4(r4)
1578 add r8,r4,r0
1593 mr r4,r3
1594 5: dcbst 0,r4
1595 add r4,r4,r6
1596 cmplw r4,r5
1599 mr r4,r3
1600 6: icbi 0,r4
1601 add r4,r4,r6
1602 cmplw r4,r5
1660 3: lwzu r4,4(r3)
1661 lwzux r0,r4,r11
1664 stw r4,0(r3)
1666 stw r0,0(r4)
1674 lwz r4,GOT(__bss_end)
1676 cmplw 0,r3,r4
1683 cmplw 0,r3,r4
1688 mr r4,r10 /* Destination Address */
1707 lwz r4,CriticalInput@got(r12)
1708 mtspr IVOR0,r4 /* 0: Critical input */
1709 lwz r4,MachineCheck@got(r12)
1710 mtspr IVOR1,r4 /* 1: Machine check */
1711 lwz r4,DataStorage@got(r12)
1712 mtspr IVOR2,r4 /* 2: Data storage */
1713 lwz r4,InstStorage@got(r12)
1714 mtspr IVOR3,r4 /* 3: Instruction storage */
1715 lwz r4,ExtInterrupt@got(r12)
1716 mtspr IVOR4,r4 /* 4: External interrupt */
1717 lwz r4,Alignment@got(r12)
1718 mtspr IVOR5,r4 /* 5: Alignment */
1719 lwz r4,ProgramCheck@got(r12)
1720 mtspr IVOR6,r4 /* 6: Program check */
1721 lwz r4,FPUnavailable@got(r12)
1722 mtspr IVOR7,r4 /* 7: floating point unavailable */
1723 lwz r4,SystemCall@got(r12)
1724 mtspr IVOR8,r4 /* 8: System call */
1726 lwz r4,Decrementer@got(r12)
1727 mtspr IVOR10,r4 /* 10: Decrementer */
1728 lwz r4,IntervalTimer@got(r12)
1729 mtspr IVOR11,r4 /* 11: Interval timer */
1730 lwz r4,WatchdogTimer@got(r12)
1731 mtspr IVOR12,r4 /* 12: Watchdog timer */
1732 lwz r4,DataTLBError@got(r12)
1733 mtspr IVOR13,r4 /* 13: Data TLB error */
1734 lwz r4,InstructionTLBError@got(r12)
1735 mtspr IVOR14,r4 /* 14: Instruction TLB error */
1736 lwz r4,DebugBreakpoint@got(r12)
1737 mtspr IVOR15,r4 /* 15: Debug */
1747 mfspr r4,L1CFG0
1748 andi. r4,r4,0x1ff
1749 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1750 mtctr r4
1783 li r4,32
1787 slw r5,r4,r5 /* r5 = cache block size */
1801 lis r4,0
1804 1: lwz r3,0(r4) /* Load... */
1805 add r4,r4,r5
1809 lis r4,0
1812 1: dcbf 0,r4 /* ...and flush. */
1813 add r4,r4,r5