Lines Matching refs:SGMII_FM1_DTSEC10
25 {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
28 {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
35 {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
37 {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
39 {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
45 {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
49 {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
53 {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
57 {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
61 {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
103 {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
106 {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
109 {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
112 {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
115 {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
118 {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
121 {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
124 {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
134 {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
137 {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
140 {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
143 {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
146 {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
154 {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,