Lines Matching refs:pic
32 volatile ccsr_pic_t *pic = &immr->im_pic; in interrupt_init_cpu() local
43 pic->gcr = MPC86xx_PICGCR_RST; in interrupt_init_cpu()
44 while (pic->gcr & MPC86xx_PICGCR_RST) in interrupt_init_cpu()
46 pic->gcr = MPC86xx_PICGCR_MODE; in interrupt_init_cpu()
55 pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ in interrupt_init_cpu()
56 debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1); in interrupt_init_cpu()
58 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ in interrupt_init_cpu()
59 debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2); in interrupt_init_cpu()
61 pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ in interrupt_init_cpu()
62 debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3); in interrupt_init_cpu()
65 pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */ in interrupt_init_cpu()
66 debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8); in interrupt_init_cpu()
69 pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */ in interrupt_init_cpu()
70 debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9); in interrupt_init_cpu()
73 pic->ctpr = 0; /* 40080 clear current task priority register */ in interrupt_init_cpu()