xref: /u-boot/arch/powerpc/include/asm/immap_86xx.h

843 typedef struct ccsr_rio {  struct
844 	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
845 	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
846 	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
847 	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
848 	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
849 	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
850 	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
851 	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
852 	char	res1[32];
853 	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
854 	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
855 	char	res2[4];
856 	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
857 	char	res3[12];
858 	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
859 	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
860 	char	res4[4];
861 	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
862 	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
863 	char	res5[144];
864 …	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
865 	char	res6[28];
866 	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
867 	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
868 	char	res7[20];
869 	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
870 	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
871 	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
872 	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
873 	char	res8[12];
874 	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
875 	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
876 	char	res9[1184];
877 	uint	erbh;		/* 0xc0600 - Error Reporting Block Header Register */
878 	char	res10[4];
879 	uint	ltledcsr;	/* 0xc0608 - Logical/Transport layer error detect status register */
880 	uint	ltleecsr;	/* 0xc060c - Logical/Transport layer error enable register */
881 	char	res11[4];
882 	uint	ltlaccsr;	/* 0xc0614 - Logical/Transport layer addresss capture register */
883 	uint	ltldidccsr;	/* 0xc0618 - Logical/Transport layer device ID capture register */
884 	uint	ltlcccsr;	/* 0xc061c - Logical/Transport layer control capture register */
885 	char	res12[32];
886 	uint	edcsr;	        /* 0xc0640 - Port 0 error detect status register */
887 	uint	erecsr;	        /* 0xc0644 - Port 0 error rate enable status register */
888 	uint	ecacsr;	        /* 0xc0648 - Port 0 error capture attributes register */
889 	uint	pcseccsr0;	/* 0xc064c - Port 0 packet/control symbol error capture register 0 */
890 	uint	peccsr1;	/* 0xc0650 - Port 0 error capture command and status register 1 */
891 	uint	peccsr2;	/* 0xc0654 - Port 0 error capture command and status register 2 */
892 	uint	peccsr3;	/* 0xc0658 - Port 0 error capture command and status register 3 */
893 	char	res13[12];
894 	uint	ercsr;	        /* 0xc0668 - Port 0 error rate command and status register */
895 	uint	ertcsr;	        /* 0xc066C - Port 0 error rate threshold status register*/
896 	char	res14[63892];
897 	uint	llcr;		/* 0xd0004 - Logical Layer Configuration Register */
898 	char	res15[12];
899 	uint	epwisr;		/* 0xd0010 - Error / Port-Write Interrupt Status Register */
900 	char	res16[12];
901 	uint	lretcr;		/* 0xd0020 - Logical Retry Error Threshold Configuration Register */
902 	char	res17[92];
903 	uint	pretcr;		/* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
904 	char	res18[124];
905 	uint	adidcsr;	/* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
906 	char	res19[28];
907 	uint	ptaacr;	        /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
908 	char	res20[12];
909 	uint	iecsr;	        /* 0xd0130 - Port 0 Implementation Error Status Register */
910 	char	res21[12];
911 	uint	pcr;		/* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
912 	char	res22[20];
913 	uint	slcsr;	        /* 0xd0158 - Port 0 Serial Link Command and Status Register */
914 	char	res23[4];
915 	uint	sleir;	        /* 0xd0160 - Port 0 Serial Link Error Injection Register */
916 	char	res24[2716];
917 	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
918 	uint	rowtear0;	/* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
919 	char	res25[8];
920 	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
921 	char	res26[12];
922 	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
923 	uint	rowtear1;	/* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
924 	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
925 	char	res27[4];
926 	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
927 	uint	rows1r1;	/* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
928 	uint	rows2r1;	/* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
929 	uint	rows3r1;	/* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
930 	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
931 	uint	rowtear2;	/* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
932 	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
933 	char	res28[4];
934 	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
935 	uint	rows1r2;	/* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
936 	uint	rows2r2;	/* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
937 	uint	rows3r2;	/* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
938 	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
939 	uint	rowtear3;	/* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
940 	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
941 	char	res29[4];
942 	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
943 	uint	rows1r3;	/* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
944 	uint	rows2r3;	/* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
945 	uint	rows3r3;	/* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
946 	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
947 	uint	rowtear4;	/* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
948 	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
949 	char	res30[4];
950 	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
951 	uint	rows1r4;	/* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
952 	uint	rows2r4;	/* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
953 	uint	rows3r4;	/* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
954 	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
955 	uint	rowtear5;	/* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
956 	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
957 	char	res31[4];
958 	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
959 	uint	rows1r5;	/* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
960 	uint	rows2r5;	/* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
961 	uint	rows3r5;	/* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
962 	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
963 	uint	rowtear6;	/* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
964 	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
965 	char	res32[4];
966 	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
967 	uint	rows1r6;	/* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
968 	uint	rows2r6;	/* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
969 	uint	rows3r6;	/* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
970 	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
971 	uint	rowtear7;	/* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
972 	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
973 	char	res33[4];
974 	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
975 	uint	rows1r7;	/* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
976 	uint	rows2r7;	/* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
977 	uint	rows3r7;	/* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
978 	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
979 	uint	rowtear8;	/* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
980 	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
981 	char	res34[4];
982 	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
983 	uint	rows1r8;	/* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
984 	uint	rows2r8;	/* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
985 	uint	rows3r8;	/* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
986 	char	res35[64];
987 	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
988 	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
989 	char	res36[4];
990 	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
991 	char	res37[12];
992 	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
993 	char	res38[4];
994 	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
995 	char	res39[4];
996 	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
997 	char	res40[12];
998 	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
999 	char	res41[4];
1000 	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1001 	char	res42[4];
1002 	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1003 	char	res43[12];
1004 	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1005 	char	res44[4];
1006 	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1007 	char	res45[4];
1008 	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1009 	char	res46[12];
1010 	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1011 	char	res47[12];
1012 	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1013 	char	res48[12];
1014 	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1015 	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1016 	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1017 	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
1018 	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1019 	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
1020 	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
1021 	char	res49[4];
1022 	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
1023 	char	res50[4];
1024 	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
1025 	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
1026 	char	res51[8656];
1027 	uint	omr;		/* 0xd3000 - Outbound Mode Register */
1028 	uint	osr;		/* 0xd3004 - Outbound Status Register */
1029 	uint	eodqtpar;	/* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1030 	uint	odqtpar;	/* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
1031 	uint	eosar;		/* 0xd3010 - Extended Outbound Unit Source Address Register */
1032 	uint	osar;		/* 0xd3014 - Outbound Unit Source Address Register */
1033 	uint	odpr;		/* 0xd3018 - Outbound Destination Port Register */
1034 	uint	odatr;		/* 0xd301c - Outbound Destination Attributes Register */
1035 	uint	odcr;		/* 0xd3020 - Outbound Doubleword Count Register */
1036 	uint	eodqhpar;	/* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1037 	uint	odqhpar;	/* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
1038 	uint	oretr;	        /* 0xd302C - Outbound Retry Error Threshold Register */
1039 	uint	omgr;	        /* 0xd3030 - Outbound Multicast Group Register */
1040 	uint	omlr;	        /* 0xd3034 - Outbound Multicast List Register */
1041 	char	res52[40];
1042 	uint	imr;		/* 0xd3060 - Outbound Mode Register */
1043 	uint	isr;		/* 0xd3064 - Inbound Status Register */
1044 	uint	eidqtpar;	/* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1045 	uint	idqtpar;	/* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
1046 	uint	eifqhpar;	/* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
1047 	uint	ifqhpar;	/* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
1071 } ccsr_rio_t;  argument

Last Index update Sat Jun 03 09:59:21 CST 2023